Joshua Wise's Git repositories - fpgaboy.git/blob

1 `define ADDR_LCDC 16'hFF40

2 `define ADDR_STAT 16'hFF41

3 `define ADDR_SCY 16'hFF42

4 `define ADDR_SCX 16'hFF43

5 `define ADDR_LY 16'hFF44

6 `define ADDR_LYC 16'hFF45

7 `define ADDR_DMA 16'hFF46

8 `define ADDR_BGP 16'hFF47

9 `define ADDR_OBP0 16'hFF48

10 `define ADDR_OBP1 16'hFF49

11 `define ADDR_WY 16'hFF4A

12 `define ADDR_WX 16'hFF4B

13

14 module LCDC(

15 input [15:0] addr,

16 inout [7:0] data,

17 input clk, // 8MHz clock

18 input wr, rd,

19 output wire lcdcirq,

20 output wire vblankirq,

21 output wire lcdclk, lcdvs, lcdhs,

22 output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);

23

24 /***** Bus latches *****/

25 reg rdlatch = 0;

26 reg [15:0] addrlatch = 0;

27

28 /***** Needed prototypes *****/

29 wire [1:0] pixdata;

30

31 /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/

32 reg clk4 = 0;

33 always @(posedge clk)

34 clk4 <= ~clk4;

35

36 /***** LCD control registers *****/

37 reg [7:0] rLCDC = 8'h00;

38 reg [7:0] rSTAT = 8'h00;

39 reg [7:0] rSCY = 8'b00;

40 reg [7:0] rSCX = 8'b00;

41 reg [7:0] rLYC = 8'b00;

42 reg [7:0] rDMA = 8'b00;

43 reg [7:0] rBGP = 8'b00;

44 reg [7:0] rOBP0 = 8'b00;

45 reg [7:0] rOBP1 = 8'b00;

46 reg [7:0] rWY = 8'b00;

47 reg [7:0] rWX = 8'b00;

48

49 /***** Sync generation *****/

50

51 /* A complete cycle takes 456 clocks.

52 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.

53 *

54 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks

55 * 1 -> in vblank and OAM/VRAM available

56 * 2 -> OAM in use - present 86 clks

57 * 3 -> OAM/VRAM in use - present 163 clks

58 * So, X = 0~162 is HActive,

59 * X = 163-369 is HBlank,

60 * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.

61 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition

62 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself

63 * [02:15:40] <Judge_> some kind of delay

64 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2

65 */

66 reg [8:0] posx = 9'h000;

67 reg [7:0] posy = 8'h00;

68

69 wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];

70 wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];

71

72 wire display = (posx > 2) && (posx < 163) && (posy < 144);

73

74 wire [1:0] mode = (posy < 144) ?

75 (vraminuse ? 2'b11 :

76 oaminuse ? 2'b10 :

77 2'b00)

78 : 2'b01;

79

80 wire [7:0] vxpos = rSCX + posx - 3;

81 wire [7:0] vypos = rSCY + posy;

82

83 assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];

84 assign lcdhs = (posx == 2) && rLCDC[7];

85 assign lcdclk = clk4;

86

87 wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;

88 wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;

89 wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;

90

91 reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;

92 assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);

93 assign vblankirq = (posx == 0 && posy == 153);

94

95 always @(posedge clk4)

96 begin

97 if (posx == 455) begin

98 posx <= 0;

99 if (posy == 153) begin

100 posy <= 0;

101 if (0 == rLYC)

102 lycirq <= 1;

103 end else begin

104 posy <= posy + 1;

105 /* Check for vblank and generate an IRQ if needed. */

106 if (posy == 143) begin

107 mode01irq <= 1;

108 end

109 if ((posy + 1) == rLYC)

110 lycirq <= 1;

111

112 end

113 end else begin

114 posx <= posx + 1;

115 if (posx == 165)

116 mode00irq <= 1;

117 else if (posx == 373)

118 mode10irq <= 1;

119 else begin

120 mode00irq <= 0;

121 mode01irq <= 0;

122 mode10irq <= 0;

123 end

124 lycirq <= 0;

125 end

126

127 lcdr <= lcdr_;

128 lcdg <= lcdg_;

129 lcdb <= lcdb_;

130 end

131

132 /***** Video RAM *****/

133 /* Base is 0x8000

134 *

135 * Tile data from 8000-8FFF or 8800-97FF

136 * Background tile maps 9800-9BFF or 9C00-9FFF

137 */

138 reg [7:0] tiledatahigh [6143:0];

139 reg [7:0] tiledatalow [6143:0];

140 reg [7:0] bgmap1 [1023:0];

141 reg [7:0] bgmap2 [1023:0];

142

143 // Upper five bits are Y coord, lower five bits are X coord

144 // The new tile number is loaded when vxpos[2:0] is 3'b110

145 // The new tile data is loaded when vxpos[2:0] is 3'b111

146 // The new tile data is latched and ready when vxpos[2:0] is 3'b000!

147 wire [7:0] vxpos_ = vxpos + 1;

148 wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};

149 reg [7:0] tileno1;

150 reg [7:0] tileno2;

151 wire [7:0] tileno = rLCDC[3] ? tileno2 : tileno1;

152 wire [11:0] tileaddr =

153 {(rLCDC[4] ? {1'b0,tileno} : (9'b100000000 + {tileno[7],tileno})),

154 vypos[2:0]};

155 reg [7:0] tilehigh, tilelow;

156 wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};

157 assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};

158

159 wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);

160 wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);

161 wire decode_bgmap2 = (addr >= 16'h9C00) && (addr <= 16'h9FFF);

162

163 wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];

164 wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];

165

166 always @(posedge clk)

167 begin

168 if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin

169 tileno1 <= bgmap1[bgmapaddr_in];

170 if (wr && decode_bgmap1 && ~vraminuse)

171 bgmap1[bgmapaddr_in] <= data;

172 end

173 if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap2) begin

174 tileno2 <= bgmap2[bgmapaddr_in];

175 if (wr && decode_bgmap2 && ~vraminuse)

176 bgmap2[bgmapaddr_in] <= data;

177 end

178 if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin

179 tilehigh <= tiledatahigh[tileaddr_in];

180 tilelow <= tiledatalow[tileaddr_in];

181 if (wr && addr[0] && decode_tiledata && ~vraminuse)

182 tiledatahigh[tileaddr_in] <= data;

183 if (wr && ~addr[0] && decode_tiledata && ~vraminuse)

184 tiledatalow[tileaddr_in] <= data;

185 end

186 end

187

188 /***** Bus interface *****/

189 assign data = rdlatch ?

190 ((addrlatch == `ADDR_LCDC) ? rLCDC :

191 (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :

192 (addrlatch == `ADDR_SCY) ? rSCY :

193 (addrlatch == `ADDR_SCX) ? rSCX :

194 (addrlatch == `ADDR_LY) ? posy :

195 (addrlatch == `ADDR_LYC) ? rLYC :

196 (addrlatch == `ADDR_BGP) ? rBGP :

197 (addrlatch == `ADDR_OBP0) ? rOBP0 :

198 (addrlatch == `ADDR_OBP1) ? rOBP1 :

199 (addrlatch == `ADDR_WY) ? rWY :

200 (addrlatch == `ADDR_WX) ? rWX :

201 (decode_tiledata && addrlatch[0]) ? tilehigh :

202 (decode_tiledata && ~addrlatch[0]) ? tilelow :

203 (decode_bgmap1) ? tileno :

204 8'bzzzzzzzz) :

205 8'bzzzzzzzz;

206

207 always @(posedge clk)

208 begin

209 rdlatch <= rd;

210 addrlatch <= addr;

211 if (wr)

212 case (addr)

213 `ADDR_LCDC: rLCDC <= data;

214 `ADDR_STAT: rSTAT <= {data[7:2],rSTAT[1:0]};

215 `ADDR_SCY: rSCY <= data;

216 `ADDR_SCX: rSCX <= data;

217 `ADDR_LYC: rLYC <= data;

218 `ADDR_DMA: rDMA <= data;

219 `ADDR_BGP: rBGP <= data;

220 `ADDR_OBP0: rOBP0 <= data;

221 `ADDR_OBP1: rOBP1 <= data;

222 `ADDR_WY: rWY <= data;

223 `ADDR_WX: rWX <= data;

224 endcase

225 end

226 endmodule