[fpgaboy.git] / Buttons.v

`define ADDR_P1 16'hFF00

/* note: buttons are 'pressed' when the input is high */

module Buttons(
        input core_clk,
        input wr,
        input rd,
        input [15:0] addr,
        inout [7:0] data,
        input [7:0] buttons,
        output reg int
        );

        reg rdlatch;
        reg [15:0] addrlatch;

        reg [7:0] p1;
        reg [3:0] oldp1013;

        assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;

        wire [3:0] p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) & (p1[5] ? 4'b1111 : ~buttons[7:4]);

        always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_P1: p1[5:4] <= data[5:4];
                        endcase
                end
                rdlatch <= rd;
                addrlatch <= addr;
                p1[3:0] <= p1013;
                oldp1013 <= p1013;
                int <= | (oldp1013 & (oldp1013 ^ p1013));
        end
endmodule