]> Joshua Wise's Git repositories - fpgaboy.git/blob - insn_jp-jpcc.v
Add bit instruction
[fpgaboy.git] / insn_jp-jpcc.v
1 `ifdef EXECUTE
2         `INSN_JP_imm,`INSN_JPCC_imm: begin
3                 case (cycle)
4                 0:      begin
5                                 `EXEC_INC_PC
6                                 `EXEC_READ(`_PC + 1)
7                         end
8                 1:      begin
9                                 `EXEC_INC_PC
10                                 `EXEC_READ(`_PC + 1)
11                         end
12                 2:      begin
13                                 `EXEC_INC_PC
14                                 if (!opcode[0]) begin   // i.e., JP cc,nn
15                                         /* We need to check the condition code to bail out. */
16                                         case (opcode[4:3])
17                                         `INSN_cc_NZ:    if (`_F[7]) `EXEC_NEWCYCLE
18                                         `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
19                                         `INSN_cc_NC:    if (`_F[4]) `EXEC_NEWCYCLE
20                                         `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE
21                                         endcase
22                                 end
23                         end
24                 3:      `EXEC_NEWCYCLE
25                 endcase
26         end
27 `endif
28
29 `ifdef WRITEBACK
30         `INSN_JP_imm,`INSN_JPCC_imm: begin
31                 case (cycle)
32                 0:      begin /* type F */ end
33                 1:      tmp <= rdata;   // tmp contains newpcl
34                 2:      tmp2 <= rdata;  // tmp2 contains newpch
35                 3:      `_PC <= {tmp2,tmp};
36                 endcase
37         end
38 `endif
This page took 0.026207 seconds and 4 git commands to generate.