Set up the bus a little before the clock.
[fpgaboy.git] / insn_ld_reg_hl.v
1 `ifdef EXECUTE
2         `INSN_LD_reg_HL: begin
3                 case(cycle)
4                 0:      `EXEC_READ(`_HL)
5                 1:      begin
6                                 `EXEC_INC_PC
7                                 `EXEC_NEWCYCLE
8                         end
9                 endcase
10         end
11 `endif
12
13 `ifdef WRITEBACK
14         `INSN_LD_reg_HL: begin
15                 case (cycle)
16                 0:      begin end
17                 1:      case (opcode[5:3])
18                         `INSN_reg_A:    `_A <= rdata;
19                         `INSN_reg_B:    `_B <= rdata;
20                         `INSN_reg_C:    `_C <= rdata;
21                         `INSN_reg_D:    `_D <= rdata;
22                         `INSN_reg_E:    `_E <= rdata;
23                         `INSN_reg_H:    `_H <= rdata;
24                         `INSN_reg_L:    `_L <= rdata;
25                         endcase
26                 endcase
27         end
28 `endif
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