JP
[fpgaboy.git] / Uart.v
1 `define IN_CLK 8388608
2 `define OUT_CLK 9600
3 `define CLK_DIV `IN_CLK / `OUT_CLK
4 `define MMAP_ADDR 16'hFF50
5
6 module UART(
7         input clk,
8         input wr,
9         input rd,
10         input [15:0] addr,
11         inout [7:0] data,
12         output reg serial);
13         
14         wire decode = (addr == `MMAP_ADDR);
15         
16         wire [7:0] odata;
17         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
18
19         reg [7:0] data_stor = 0;
20         reg [15:0] clkdiv = 0;
21         reg have_data = 0;
22         reg data_end = 0;
23         reg [3:0] diqing = 4'b0000;
24         
25         wire new = (wr) && (!have_data) && decode;
26         
27         assign odata = have_data ? 8'b1 : 8'b0;
28
29         always @ (negedge clk)
30         begin
31                 /* deal with diqing */
32                 if(new) begin
33                         data_stor <= data;
34                         have_data <= 1;
35                         diqing <= 4'b0000;
36                 end else if (clkdiv == 0) begin
37                         diqing <= diqing + 1;
38                         if (have_data)
39                                 case (diqing)
40                                 4'b0000: serial <= 0;
41                                 4'b0001: serial <= data_stor[0];
42                                 4'b0010: serial <= data_stor[1];
43                                 4'b0011: serial <= data_stor[2];
44                                 4'b0100: serial <= data_stor[3];
45                                 4'b0101: serial <= data_stor[4];
46                                 4'b0110: serial <= data_stor[5];
47                                 4'b0111: serial <= data_stor[6];
48                                 4'b1000: serial <= data_stor[7];
49                                 4'b1001: serial <= 1;
50                                 4'b1010: have_data <= 0;
51                                 default: $stop;
52                         endcase
53                 end
54
55                 /* deal with clkdiv */
56                 if((new && !have_data) || clkdiv == `CLK_DIV)
57                         clkdiv <= 0;
58                 else
59                         clkdiv <= clkdiv + 1;
60         end
61 endmodule
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