RETCC that breaks everything. Why?
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [2047:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[11:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module InternalRAM(
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         // synthesis attribute ram_style of reg is block
25         reg [7:0] ram [8191:0];
26         
27         wire decode = address[15:13] == 3'b110;
28         reg [7:0] odata;
29         wire idata = data;
30         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
31         
32         always @(negedge clk)
33         begin
34                 if (decode)     // This has to go this way. The only way XST knows how to do
35                 begin                           // block ram is chip select, write enable, and always
36                         if (wr)         // reading. "else if rd" does not cut it ...
37                                 ram[address[12:0]] <= data;
38                         odata <= ram[address[12:0]];
39                 end
40         end
41 endmodule
42
43 module Switches(
44         input [15:0] address,
45         inout [7:0] data,
46         input clk,
47         input wr, rd,
48         input [7:0] switches,
49         output reg [7:0] ledout);
50         
51         wire decode = address == 16'hFF51;
52         reg [7:0] odata;
53         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
54         
55         always @(negedge clk)
56         begin
57                 if (decode && rd)
58                         odata <= switches;
59                 else if (decode && wr)
60                         ledout <= data;
61         end
62 endmodule
63
64 module CoreTop(
65         input xtal,
66         input [7:0] switches,
67         input [3:0] buttons,
68         output wire [7:0] leds,
69         output serio,
70         output wire [3:0] digits,
71         output wire [7:0] seven);
72         
73         wire clk;
74         //IBUFG ibuf (.O(clk), .I(iclk));
75         
76         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
77
78         wire [15:0] addr;       
79         wire [7:0] data;
80         wire wr, rd;
81
82         GBZ80Core core(
83                 .clk(clk),
84                 .busaddress(addr),
85                 .busdata(data),
86                 .buswr(wr),
87                 .busrd(rd));
88         
89         ROM rom(
90                 .address(addr),
91                 .data(data),
92                 .clk(clk),
93                 .wr(wr),
94                 .rd(rd));
95         
96         AddrMon amon(
97     .addr(addr), 
98     .clk(clk), 
99     .digit(digits), 
100     .out(seven),
101          .freeze(buttons[0])
102     );
103          
104         Switches sw(
105                 .address(addr),
106                 .data(data),
107                 .clk(clk),
108                 .wr(wr),
109                 .rd(rd),
110                 .ledout(leds),
111                 .switches(switches)
112                 );
113
114         UART nouart (
115     .clk(clk), 
116     .wr(wr), 
117     .rd(rd), 
118     .addr(addr), 
119     .data(data), 
120     .serial(serio)
121     );
122
123   InternalRAM ram(
124                 .address(addr),
125                 .data(data),
126                 .clk(clk),
127                 .wr(wr),
128                 .rd(rd));
129 endmodule
130
131 module TestBench();
132         reg clk = 0;
133         wire [15:0] addr;
134         wire [7:0] data;
135         wire wr, rd;
136         
137 //      wire [7:0] leds;
138 //      wire [7:0] switches;
139         
140         always #10 clk <= ~clk;
141         GBZ80Core core(
142                 .clk(clk),
143                 .busaddress(addr),
144                 .busdata(data),
145                 .buswr(wr),
146                 .busrd(rd));
147         
148         ROM rom(
149                 .clk(clk),
150                 .address(addr),
151                 .data(data),
152                 .wr(wr),
153                 .rd(rd));
154         
155         InternalRAM ram(
156                 .address(addr),
157                 .data(data),
158                 .clk(clk),
159                 .wr(wr),
160                 .rd(rd));
161
162         wire serio;
163         UART uart(
164                 .addr(addr),
165                 .data(data),
166                 .clk(clk),
167                 .wr(wr),
168                 .rd(rd),
169                 .serial(serio));
170         
171 //      Switches sw(
172 //              .clk(clk),
173 //              .address(addr),
174 //              .data(data),
175 //              .wr(wr),
176 //              .rd(rd),
177 //              .switches(switches),
178 //              .leds(leds));
179 endmodule
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