Add mock up LCDC
[fpgaboy.git] / LCDC.v
1 `define ADDR_LCDC       16'hFF40
2 `define ADDR_STAT       16'hFF41
3 `define ADDR_SCY        16'hFF42
4 `define ADDR_SCX        16'hFF43
5 `define ADDR_LY         16'hFF44
6 `define ADDR_LYC        16'hFF45
7 `define ADDR_DMA        16'hFF46
8 `define ADDR_BGP        16'hFF47
9 `define ADDR_OBP0       16'hFF48
10 `define ADDR_OBP1       16'hFF49
11 `define ADDR_WY         16'hFF4A
12 `define ADDR_WX         16'hFF4B
13
14 module LCDC(
15         input [15:0] addr,
16         inout [7:0] data,
17         input clk,      // 8MHz clock
18         input wr, rd,
19         output reg irq = 0);
20         
21         /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
22         reg clk4 = 0;
23         always @(posedge clk)
24                 clk4 = ~clk4;
25         
26         /***** Sync generation *****/
27         
28         /* A complete cycle takes 456 clocks.
29          * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
30          *
31          * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
32          *        1 -> in vblank and OAM/VRAM available
33          *        2 -> OAM in use - present 83 clks
34          *        3 -> OAM/VRAM in use - present 166 clks
35          * So, X = 0~165 is HActive,
36          * X = 166-372 is HBlank,
37          * X = 373-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
38          */
39         reg [8:0] posx = 9'h000;
40         reg [7:0] posy = 8'h00;
41         wire [1:0] mode = (posy < 144) ?
42                                 ((posx < 166) ? 2'b11 :
43                                  (posx < 373) ? 2'b00 :
44                                  2'b10)
45                                 : 2'b01;
46         
47         always @(posedge clk)
48         begin
49                 if (posx == 455) begin
50                         posx <= 0;
51                         if (posy == 153)
52                                 posy <= 0;
53                         else
54                                 posy <= posy + 1;
55                 end else
56                         posx <= posx + 1;
57         end
58   
59         /***** Bus interface *****/
60         reg [7:0] rLCDC = 8'h91;
61         reg [7:0] rSTAT = 8'h00;
62         reg [7:0] rSCY = 8'b00;
63         reg [7:0] rSCX = 8'b00;
64         reg [7:0] rLYC = 8'b00;
65         reg [7:0] rDMA = 8'b00;
66         reg [7:0] rBGP = 8'b00;
67         reg [7:0] rOBP0 = 8'b00;
68         reg [7:0] rOBP1 = 8'b00;
69         reg [7:0] rWY = 8'b00;
70         reg [7:0] rWX = 8'b00;
71         
72         assign data = rd ?
73                         (addr == `ADDR_LCDC) ? rLCDC :
74                         (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
75                         (addr == `ADDR_SCY) ? rSCY :
76                         (addr == `ADDR_SCX) ? rSCX :
77                         (addr == `ADDR_LY) ? posy :
78                         (addr == `ADDR_LYC) ? rLYC :
79                         (addr == `ADDR_BGP) ? rBGP :
80                         (addr == `ADDR_OBP0) ? rOBP0 :
81                         (addr == `ADDR_OBP1) ? rOBP1 :
82                         (addr == `ADDR_WY) ? rWY :
83                         (addr == `ADDR_WX) ? rWX :
84                         8'bzzzzzzzz :
85                 8'bzzzzzzzz;
86   
87         always @(negedge clk)
88         begin
89                 if (wr)
90                         case (addr)
91                         `ADDR_LCDC:     rLCDC <= data;
92                         `ADDR_STAT:     rSTAT <= {data[7:2],rSTAT[1:0]};
93                         `ADDR_SCY:      rSCY <= data;
94                         `ADDR_SCX:      rSCX <= data;
95                         `ADDR_LYC:      rLYC <= data;
96                         `ADDR_DMA:      rDMA <= data;
97                         `ADDR_BGP:      rBGP <= data;
98                         `ADDR_OBP0:     rOBP0 <= data;
99                         `ADDR_OBP1:     rOBP1 <= data;
100                         `ADDR_WY:       rWY <= data;
101                         `ADDR_WX:       rWX <= data;
102                         endcase
103         end
104 endmodule
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