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[fpgaboy.git] / core / insn_ld_reg_imm8.v
1 `define INSN_LD_reg_imm8        9'b000xxx110
2
3 `ifdef EXECUTE
4         `INSN_LD_reg_imm8: begin
5                 case (cycle)
6                 0:      begin
7                                 `EXEC_INC_PC
8                                 `EXEC_READ(`_PC + 1)
9                         end
10                 1:      begin
11                                 `EXEC_INC_PC
12                                 if (opcode[5:3] == `INSN_reg_dHL)
13                                         `EXEC_WRITE(`_HL, rdata)
14                                 else
15                                         `EXEC_NEWCYCLE
16                         end
17                 2:      `EXEC_NEWCYCLE
18                 endcase
19         end
20 `endif
21
22 `ifdef WRITEBACK
23         `INSN_LD_reg_imm8:
24                 case (cycle)
25                 0:      begin end
26                 1:      case (opcode[5:3])
27                         `INSN_reg_A:    begin `_A <= rdata; end
28                         `INSN_reg_B:    begin `_B <= rdata; end
29                         `INSN_reg_C:    begin `_C <= rdata; end
30                         `INSN_reg_D:    begin `_D <= rdata; end
31                         `INSN_reg_E:    begin `_E <= rdata; end
32                         `INSN_reg_H:    begin `_H <= rdata; end
33                         `INSN_reg_L:    begin `_L <= rdata; end
34                         `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
35                         endcase
36                 2:      begin end
37                 endcase
38 `endif
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