ARP responder
[fpgaboy.git] / core / insn_incdec_reg8.v
1 `define INSN_INCDEC_reg8        9'b000xxx10x
2
3 `ifdef EXECUTE
4         `INSN_INCDEC_reg8: begin
5                 `EXEC_INC_PC
6                 `EXEC_NEWCYCLE
7                 case (opcode[5:3])
8                 `INSN_reg_A:    tmp <= `_A + (opcode[0] ? 8'hFF : 8'h01);
9                 `INSN_reg_B:    tmp <= `_B + (opcode[0] ? 8'hFF : 8'h01);
10                 `INSN_reg_C:    tmp <= `_C + (opcode[0] ? 8'hFF : 8'h01);
11                 `INSN_reg_D:    tmp <= `_D + (opcode[0] ? 8'hFF : 8'h01);
12                 `INSN_reg_E:    tmp <= `_E + (opcode[0] ? 8'hFF : 8'h01);
13                 `INSN_reg_H:    tmp <= `_H + (opcode[0] ? 8'hFF : 8'h01);
14                 `INSN_reg_L:    tmp <= `_L + (opcode[0] ? 8'hFF : 8'h01);
15                 endcase
16         end
17 `endif
18
19 `ifdef WRITEBACK
20         `INSN_INCDEC_reg8: begin
21                 case (opcode[5:3])
22                 `INSN_reg_A:    `_A <= tmp;
23                 `INSN_reg_B:    `_B <= tmp;
24                 `INSN_reg_C:    `_C <= tmp;
25                 `INSN_reg_D:    `_D <= tmp;
26                 `INSN_reg_E:    `_E <= tmp;
27                 `INSN_reg_H:    `_H <= tmp;
28                 `INSN_reg_L:    `_L <= tmp;
29                 endcase
30                 `_F <= {
31                                 (tmp == 8'h00) ? 1'b1 : 1'b0,   /* Z */
32                                 opcode[0],       /* N */
33                                 (tmp[3:0] == (opcode[0] ? 4'hF : 4'h0)) ? 1'b1 : 1'b0,
34                                 `_F[4:0]
35                         };
36         end
37 `endif
This page took 0.019286 seconds and 4 git commands to generate.