Video RAM cut 1 -- on distributed ram
[fpgaboy.git] / LCDC.v
1 `define ADDR_LCDC       16'hFF40
2 `define ADDR_STAT       16'hFF41
3 `define ADDR_SCY        16'hFF42
4 `define ADDR_SCX        16'hFF43
5 `define ADDR_LY         16'hFF44
6 `define ADDR_LYC        16'hFF45
7 `define ADDR_DMA        16'hFF46
8 `define ADDR_BGP        16'hFF47
9 `define ADDR_OBP0       16'hFF48
10 `define ADDR_OBP1       16'hFF49
11 `define ADDR_WY         16'hFF4A
12 `define ADDR_WX         16'hFF4B
13
14 module LCDC(
15         input [15:0] addr,
16         inout [7:0] data,
17         input clk,      // 8MHz clock
18         input wr, rd,
19         output wire lcdcirq,
20         output wire vblankirq,
21         output wire lcdclk, lcdvs, lcdhs,
22         output wire [2:0] lcdr, lcdg, output wire [1:0] lcdb);
23         
24         /***** Needed prototypes *****/
25         wire [1:0] pixdata;
26         
27         /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
28         reg clk4 = 0;
29         always @(posedge clk)
30                 clk4 = ~clk4;
31         assign lcdclk = clk4;
32         
33         /***** LCD control registers *****/
34         reg [7:0] rLCDC = 8'h91;
35         reg [7:0] rSTAT = 8'h00;
36         reg [7:0] rSCY = 8'b00;
37         reg [7:0] rSCX = 8'b00;
38         reg [7:0] rLYC = 8'b00;
39         reg [7:0] rDMA = 8'b00;
40         reg [7:0] rBGP = 8'b00;
41         reg [7:0] rOBP0 = 8'b00;
42         reg [7:0] rOBP1 = 8'b00;
43         reg [7:0] rWY = 8'b00;
44         reg [7:0] rWX = 8'b00;
45         
46         /***** Sync generation *****/
47         
48         /* A complete cycle takes 456 clocks.
49          * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
50          *
51          * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
52          *        1 -> in vblank and OAM/VRAM available
53          *        2 -> OAM in use - present 86 clks
54          *        3 -> OAM/VRAM in use - present 163 clks
55          * So, X = 0~162 is HActive,
56          * X = 163-369 is HBlank,
57          * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
58          * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
59          * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
60          * [02:15:40] <Judge_> some kind of delay
61          * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
62          */
63         reg [8:0] posx = 9'h000;
64         reg [7:0] posy = 8'h00;
65         
66         wire vraminuse = (posx < 163);
67         wire oaminuse = (posx > 369);
68         
69         wire display = (posx > 2) && (posx < 163) && (posy < 144);
70         
71         wire [1:0] mode = (posy < 144) ?
72                                 (vraminuse ? 2'b11 :
73                                  oaminuse ? 2'b10 :
74                                  2'b00)
75                                 : 2'b01;
76         
77         assign lcdvs = (posy == 153) && (posx == 455);
78         assign lcdhs = (posx == 455);
79         assign lcdr = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
80         assign lcdg = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
81         assign lcdb = display ? {posy < rSCY ? 2'b11 : 2'b00} : 2'b00;
82         
83         reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
84         assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
85         assign vblankirq = (posx == 0 && posy == 153);
86         
87         always @(posedge clk4)
88         begin
89                 if (posx == 455) begin
90                         posx <= 0;
91                         if (posy == 153) begin
92                                 posy <= 0;
93                                 if (0 == rLYC)
94                                         lycirq <= 1;
95                         end else begin
96                                 posy <= posy + 1;
97                                 /* Check for vblank and generate an IRQ if needed. */
98                                 if (posy == 143) begin 
99                                         mode01irq <= 1;
100                                 end
101                                 if ((posy + 1) == rLYC)
102                                         lycirq <= 1;
103                                 
104                         end
105                 end else begin
106                         posx <= posx + 1;
107                         if (posx == 165)
108                                 mode00irq <= 1;
109                         else if (posx == 373)
110                                 mode10irq <= 1;
111                         else begin
112                                 mode00irq <= 0;
113                                 mode01irq <= 0;
114                                 mode10irq <= 0;
115                         end
116                         lycirq <= 0;
117                 end
118         end
119         
120         /***** Video RAM *****/
121         /* Base is 0x8000
122          *
123          * Tile data from 8000-8FFF or 8800-97FF
124          * Background tile maps 9800-9BFF or 9C00-9FFF
125          */
126         reg [7:0] tiledata [6143:0];
127         reg [7:0] bgmap1 [1023:0];
128         reg [7:0] bgmap2 [1023:0];
129         
130         // Upper five bits are Y coord, lower five bits are X coord
131         wire [7:0] vxpos = rSCX + posx - 3;
132         wire [7:0] vypos = rSCY + posy;
133         
134         // The new tile number is loaded when vxpos[2:0] is 3'b101
135         // The new tile data low is loaded when vxpos[2:0] is 3'b110
136         // The new tile data high is loaded when vxpos[2:0] is 3'b111
137         // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
138         wire [9:0] bgmapaddr = {vypos[7:3], vxpos[7:3]};
139         reg [7:0] tileno;
140         wire [10:0] tileaddr = {tileno, vypos[2:1]};
141         reg [7:0] tilelowtmp, tilehigh, tilelow;
142         assign pixdata = {tilehigh[vxpos[2:0]], tilelow[vxpos[2:0]]};
143         
144         wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
145         wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
146         
147         always @(negedge clk)
148                 if (vraminuse) begin
149                         if ((posx == 0) || ((posx > 2) && (vxpos[2:0] == 3'b101)))
150                                 tileno <= bgmap1[bgmapaddr];
151                         else if ((posx == 1) || ((posx > 2) && (vxpos[2:0] == 3'b110)))
152                                 tilelowtmp <= tiledata[{tileaddr, 1'b0}];
153                         else if ((posx == 2) || ((posx > 2) && (vxpos[2:0] == 3'b111))) begin
154                                 tilehigh <= tiledata[{tileaddr, 1'b1}];
155                                 tilelow <= tilelowtmp;
156                         end
157                 end else begin
158                         if (decode_tiledata) begin
159                                 tilelowtmp <= tiledata[addr[12:0]];
160                                 if (wr)
161                                         tiledata[addr[12:0]] <= data;
162                         end else if (decode_bgmap1) begin
163                                 tileno <= bgmap1[addr[12:0]];
164                                 if (wr)
165                                         bgmap1[addr[12:0]] <= data;
166                         end
167                 end
168   
169         /***** Bus interface *****/
170         assign data = rd ?
171                         (addr == `ADDR_LCDC) ? rLCDC :
172                         (addr == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
173                         (addr == `ADDR_SCY) ? rSCY :
174                         (addr == `ADDR_SCX) ? rSCX :
175                         (addr == `ADDR_LY) ? posy :
176                         (addr == `ADDR_LYC) ? rLYC :
177                         (addr == `ADDR_BGP) ? rBGP :
178                         (addr == `ADDR_OBP0) ? rOBP0 :
179                         (addr == `ADDR_OBP1) ? rOBP1 :
180                         (addr == `ADDR_WY) ? rWY :
181                         (addr == `ADDR_WX) ? rWX :
182                         (decode_tiledata) ? tilelowtmp :
183                         (decode_bgmap1) ? tileno :
184                         8'bzzzzzzzz :
185                 8'bzzzzzzzz;
186   
187         always @(negedge clk)
188         begin
189                 if (wr)
190                         case (addr)
191                         `ADDR_LCDC:     rLCDC <= data;
192                         `ADDR_STAT:     rSTAT <= {data[7:2],rSTAT[1:0]};
193                         `ADDR_SCY:      rSCY <= data;
194                         `ADDR_SCX:      rSCX <= data;
195                         `ADDR_LYC:      rLYC <= data;
196                         `ADDR_DMA:      rDMA <= data;
197                         `ADDR_BGP:      rBGP <= data;
198                         `ADDR_OBP0:     rOBP0 <= data;
199                         `ADDR_OBP1:     rOBP1 <= data;
200                         `ADDR_WY:       rWY <= data;
201                         `ADDR_WX:       rWX <= data;
202                         endcase
203         end
204 endmodule
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