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[fpgaboy.git] / insn_ld_reg_imm8.v
1 `ifdef EXECUTE
2         `INSN_LD_reg_imm8: begin
3                 case (cycle)
4                 0:      begin
5                                 `EXEC_INC_PC
6                                 `EXEC_READ(`_PC + 1)
7                         end
8                 1:      begin
9                                 `EXEC_INC_PC
10                                 if (opcode[5:3] == `INSN_reg_dHL)
11                                         `EXEC_WRITE(`_HL, rdata)
12                                 else
13                                         `EXEC_NEWCYCLE
14                         end
15                 2:      `EXEC_NEWCYCLE
16                 endcase
17         end
18 `endif
19
20 `ifdef WRITEBACK
21         `INSN_LD_reg_imm8:
22                 case (cycle)
23                 0:      begin end
24                 1:      case (opcode[5:3])
25                         `INSN_reg_A:    begin `_A <= rdata; end
26                         `INSN_reg_B:    begin `_B <= rdata; end
27                         `INSN_reg_C:    begin `_C <= rdata; end
28                         `INSN_reg_D:    begin `_D <= rdata; end
29                         `INSN_reg_E:    begin `_E <= rdata; end
30                         `INSN_reg_H:    begin `_H <= rdata; end
31                         `INSN_reg_L:    begin `_L <= rdata; end
32                         `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
33                         endcase
34                 2:      begin end
35                 endcase
36 `endif
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