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Video RAM and a makefile change
[fpgaboy.git] / CoreTop.prj
1 verilog work "Uart.v"
2 verilog work "Timer.v"
3 verilog work "Interrupt.v"
4 verilog work "GBZ80Core.v"
5 verilog work "CPUDCM.v"
6 verilog work "7seg.v"
7 verilog work "System.v"
8 verilog work "LCDC.v"
9 verilog work "Framebuffer.v"
10 verilog work "pixDCM.v"
Partial Nintendo GameBoy / GBZ80 implementation on a Xilinx FPGA
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