Add list of broken tests
[fpgaboy.git] / Buttons.v
1 `define ADDR_P1 16'hFF00
2
3 /* note: buttons are 'pressed' when the input is high */
4
5 module Buttons(
6         input core_clk,
7         input wr,
8         input rd,
9         input [15:0] addr,
10         inout [7:0] data,
11         input [7:0] buttons,
12         output reg int
13         );
14
15         reg rdlatch;
16         reg [15:0] addrlatch;
17
18         reg [7:0] p1;
19         reg [3:0] oldp1013;
20
21         assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
22
23         wire [3:0] p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) & (p1[5] ? 4'b1111 : ~buttons[7:4]);
24
25         always @ (posedge core_clk) begin
26                 if(wr) begin
27                         case(addr)
28                         `ADDR_P1: p1[5:4] <= data[5:4];
29                         endcase
30                 end
31                 rdlatch <= rd;
32                 addrlatch <= addr;
33                 p1[3:0] <= p1013;
34                 oldp1013 <= p1013;
35                 int <= | (oldp1013 & (oldp1013 ^ p1013));
36         end
37 endmodule
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