]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - insn_ret-retcc.v
Remove gated clock and hence remove S.
[fpgaboy.git] / insn_ret-retcc.v
... / ...
CommitLineData
1`ifdef EXECUTE
2 `INSN_RET,`INSN_RETCC: begin
3 case (cycle)
4 0: `EXEC_READ(`_SP)
5 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret!
6 `EXEC_INC_PC // cycle 1 is skipped if we are not retcc
7 case (opcode[4:3])
8 `INSN_cc_NZ: if (registers[`REG_F][7]) `EXEC_NEWCYCLE
9 `INSN_cc_Z: if (~registers[`REG_F][7]) `EXEC_NEWCYCLE
10 `INSN_cc_NC: if (registers[`REG_F][4]) `EXEC_NEWCYCLE
11 `INSN_cc_C: if (~registers[`REG_F][4]) `EXEC_NEWCYCLE
12 endcase
13 `EXEC_READ(`_SP) // retry the read
14 end
15 2: `EXEC_READ(`_SP + 1)
16 3: begin /* twiddle thumbs */ end
17 4: `EXEC_NEWCYCLE
18 endcase
19 end
20`endif
21
22`ifdef WRITEBACK
23 `INSN_RET,`INSN_RETCC: begin
24 case (cycle)
25 0: if (opcode[0]) // i.e., not RETCC
26 cycle <= 1; // Skip cycle 1; it gets incremented on the next round.
27 1: begin /* Nothing need happen here. */ end
28 2: `_PCL <= rdata;
29 3: `_PCH <= rdata;
30 4: begin
31 `_SP <= `_SP + 2;
32 if (opcode[4] && opcode[0]) /* RETI */
33 ie <= 1;
34 end
35 endcase
36 end
37`endif
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