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1YET UNIMPLEMENTED:
2
3imm3 = 3-bit immediate value in 8 bits
4imm8 = 8-bit immediate value
5imm16 = 16-bit immediate value
616m8 = 8-bit value at the 16-bit address
78m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
8
9bits insn notes
100000 1000 LD 16m16,SP loads SP
110001 0000 STOP
120111 0110 HALT Danger! Helvetica!
131100 1011 - - - see two-byte opcodes below
141110 1000 ADD SP, imm8
151111 1000 LDHL SP, imm8 load SP+n (signed n) into HL
16
17*****************************
18
19fucking two-byte opcodes
20
21bits insn notes
221100 1011 0000 0000 RLC B
231100 1011 0000 0001 RLC C
241100 1011 0000 0010 RLC D
251100 1011 0000 0011 RLC E
261100 1011 0000 0100 RLC H
271100 1011 0000 0101 RLC L
281100 1011 0000 0110 RLC (HL)
291100 1011 0000 0111 RLC A
30
311100 1011 0000 1000 RRC B
321100 1011 0000 1001 RRC C
331100 1011 0000 1010 RRC D
341100 1011 0000 1011 RRC E
351100 1011 0000 1100 RRC H
361100 1011 0000 1101 RRC L
371100 1011 0000 1110 RRC (HL)
381100 1011 0000 1111 RRC A
39
401100 1011 0001 0000 RL B
411100 1011 0001 0001 RL C
421100 1011 0001 0010 RL D
431100 1011 0001 0011 RL E
441100 1011 0001 0100 RL H
451100 1011 0001 0101 RL L
461100 1011 0001 0110 RL (HL)
471100 1011 0001 0111 RL A
48
491100 1011 0001 1000 RR B
501100 1011 0001 1001 RR C
511100 1011 0001 1010 RR D
521100 1011 0001 1011 RR E
531100 1011 0001 1100 RR H
541100 1011 0001 1101 RR L
551100 1011 0001 1110 RR (HL)
561100 1011 0001 1111 RR A
57
581100 1011 0010 0000 SLA B
591100 1011 0010 0001 SLA C
601100 1011 0010 0010 SLA D
611100 1011 0010 0011 SLA E
621100 1011 0010 0100 SLA H
631100 1011 0010 0101 SLA L
641100 1011 0010 0110 SLA (HL)
651100 1011 0010 0111 SLA A
66
671100 1011 0010 1000 SRA B
681100 1011 0010 1001 SRA C
691100 1011 0010 1010 SRA D
701100 1011 0010 1011 SRA E
711100 1011 0010 1100 SRA H
721100 1011 0010 1101 SRA L
731100 1011 0010 1110 SRA (HL)
741100 1011 0010 1111 SRA A
75
761100 1011 0011 1000 SRL B
771100 1011 0011 1001 SRL C
781100 1011 0011 1010 SRL D
791100 1011 0011 1011 SRL E
801100 1011 0011 1100 SRL H
811100 1011 0011 1101 SRL L
821100 1011 0011 1110 SRL (HL)
831100 1011 0011 1111 SRL A
84
851100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte
861100 1011 0011 0001 SWAP C
871100 1011 0011 0010 SWAP D
881100 1011 0011 0011 SWAP E
891100 1011 0011 0100 SWAP H
901100 1011 0011 0101 SWAP L
911100 1011 0011 0110 SWAP (HL)
921100 1011 0011 0111 SWAP A
93
941100 1011 1000 0000 RES imm3, B reset bit specified by imm3
951100 1011 1000 0001 RES imm3, C
961100 1011 1000 0010 RES imm3, D
971100 1011 1000 0011 RES imm3, E
981100 1011 1000 0100 RES imm3, H
991100 1011 1000 0101 RES imm3, L
1001100 1011 1000 0110 RES imm3, (HL)
1011100 1011 1000 0111 RES imm3, A
102
1031100 1011 1100 0000 SET imm3, B set bit specified by imm3
1041100 1011 1100 0001 SET imm3, C
1051100 1011 1100 0010 SET imm3, D
1061100 1011 1100 0011 SET imm3, E
1071100 1011 1100 0100 SET imm3, H
1081100 1011 1100 0101 SET imm3, L
1091100 1011 1100 0110 SET imm3, (HL)
1101100 1011 1100 0111 SET imm3, A
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