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[fpgaboy.git] / core / insn_bit.v
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CommitLineData
1`define INSN_BIT 9'b101xxxxxx
2
3`ifdef EXECUTE
4 `INSN_BIT: begin
5 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
6 `EXEC_READ(`_HL)
7 end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 2)) begin
8 `EXEC_NEWCYCLE
9 end else begin
10 `EXEC_INC_PC
11 case (opcode[2:0])
12 `INSN_reg_A: tmp <= `_A;
13 `INSN_reg_B: tmp <= `_B;
14 `INSN_reg_C: tmp <= `_C;
15 `INSN_reg_D: tmp <= `_D;
16 `INSN_reg_E: tmp <= `_E;
17 `INSN_reg_H: tmp <= `_H;
18 `INSN_reg_L: tmp <= `_L;
19 `INSN_reg_dHL: tmp <= rdata;
20 endcase
21 if (opcode[2:0] != `INSN_reg_dHL) begin
22 `EXEC_NEWCYCLE
23 end
24 end
25 end
26`endif
27
28`ifdef WRITEBACK
29 `INSN_BIT: begin
30 if ((opcode[2:0] != `INSN_reg_dHL) || (cycle == 1))
31 `_F <= {~tmp[opcode[5:3]], 2'b01, `_F[4:0]};
32 end
33`endif
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