IP

[fpgaboy.git] / core / insn_incdec_reg8.v

`define INSN_INCDEC_reg8	9'b000xxx10x

`ifdef EXECUTE
	`INSN_INCDEC_reg8: begin
		`EXEC_INC_PC
		`EXEC_NEWCYCLE
		case (opcode[5:3])
		`INSN_reg_A:	tmp <= `_A + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_B:	tmp <= `_B + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_C:	tmp <= `_C + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_D:	tmp <= `_D + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_E:	tmp <= `_E + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_H:	tmp <= `_H + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_L:	tmp <= `_L + (opcode[0] ? 8'hFF : 8'h01);
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_INCDEC_reg8: begin
		case (opcode[5:3])
		`INSN_reg_A:	`_A <= tmp;
		`INSN_reg_B:	`_B <= tmp;
		`INSN_reg_C:	`_C <= tmp;
		`INSN_reg_D:	`_D <= tmp;
		`INSN_reg_E:	`_E <= tmp;
		`INSN_reg_H:	`_H <= tmp;
		`INSN_reg_L:	`_L <= tmp;
		endcase
		`_F <= {
				(tmp == 8'h00) ? 1'b1 : 1'b0,	/* Z */
				opcode[0],	 /* N */
				(tmp[3:0] == (opcode[0] ? 4'hF : 4'h0)) ? 1'b1 : 1'b0,
				`_F[4:0]
			};
	end
`endif