]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - core/insn_jr-jrcc.v
Fix add sp, imm8 *sweatdrop*
[fpgaboy.git] / core / insn_jr-jrcc.v
... / ...
CommitLineData
1`define INSN_JR_imm 9'b000011000
2`define INSN_JRCC_imm 9'b0001xx000
3
4`ifdef EXECUTE
5 `INSN_JR_imm,`INSN_JRCC_imm: begin
6 case (cycle)
7 0: begin
8 `EXEC_INC_PC
9 `EXEC_READ(`_PC + 1)
10 end
11 1: begin
12 `EXEC_INC_PC
13 if (opcode[5]) begin // i.e., JP cc,nn
14 /* We need to check the condition code to bail out. */
15 case (opcode[4:3])
16 `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE
17 `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE
18 `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE
19 `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE
20 endcase
21 end
22 end
23 2: `EXEC_NEWCYCLE
24 endcase
25 end
26`endif
27
28`ifdef WRITEBACK
29 `INSN_JR_imm,`INSN_JRCC_imm: begin
30 case (cycle)
31 0: begin /* type F */ end
32 1: tmp <= rdata;
33 2: `_PC <= `_PC + {tmp[7]?8'hFF:8'h00,tmp};
34 endcase
35 end
36`endif
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