]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - core/insn_incdec16.v
Fix add sp, imm8 *sweatdrop*
[fpgaboy.git] / core / insn_incdec16.v
... / ...
CommitLineData
1`define INSN_INCDEC16 9'b000xxx011
2
3`ifdef EXECUTE
4 `INSN_INCDEC16: begin
5 case (cycle)
6 0: case (opcode[5:4])
7 `INSN_reg16_BC: {tmp,tmp2} <= `_BC;
8 `INSN_reg16_DE: {tmp,tmp2} <= `_DE;
9 `INSN_reg16_HL: {tmp,tmp2} <= `_HL;
10 `INSN_reg16_SP: {tmp,tmp2} <= `_SP;
11 endcase
12 1: begin
13 `EXEC_INC_PC
14 `EXEC_NEWCYCLE
15 end
16 endcase
17 end
18`endif
19
20`ifdef WRITEBACK
21 `INSN_INCDEC16: begin
22 case (cycle)
23 0: {tmp,tmp2} <= {tmp,tmp2} +
24 (opcode[3] ? 16'hFFFF : 16'h0001);
25 1: case (opcode[5:4])
26 `INSN_reg16_BC: `_BC <= {tmp,tmp2};
27 `INSN_reg16_DE: `_DE <= {tmp,tmp2};
28 `INSN_reg16_HL: `_HL <= {tmp,tmp2};
29 `INSN_reg16_SP: `_SP <= {tmp,tmp2};
30 endcase
31 endcase
32 end
33`endif
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