]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - insn_jr-jrcc.v
Fix tileaddr bug. Make bus interface more explicit.
[fpgaboy.git] / insn_jr-jrcc.v
... / ...
CommitLineData
1`ifdef EXECUTE
2 `INSN_JR_imm,`INSN_JRCC_imm: begin
3 case (cycle)
4 0: begin
5 `EXEC_INC_PC
6 `EXEC_READ(`_PC + 1)
7 end
8 1: begin
9 `EXEC_INC_PC
10 if (opcode[5]) begin // i.e., JP cc,nn
11 /* We need to check the condition code to bail out. */
12 case (opcode[4:3])
13 `INSN_cc_NZ: if (`_F[7]) `EXEC_NEWCYCLE
14 `INSN_cc_Z: if (~`_F[7]) `EXEC_NEWCYCLE
15 `INSN_cc_NC: if (`_F[4]) `EXEC_NEWCYCLE
16 `INSN_cc_C: if (~`_F[4]) `EXEC_NEWCYCLE
17 endcase
18 end
19 end
20 2: `EXEC_NEWCYCLE
21 endcase
22 end
23`endif
24
25`ifdef WRITEBACK
26 `INSN_JR_imm,`INSN_JRCC_imm: begin
27 case (cycle)
28 0: begin /* type F */ end
29 1: tmp <= rdata;
30 2: `_PC <= `_PC + {tmp[7]?8'hFF:8'h00,tmp};
31 endcase
32 end
33`endif
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