]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - insn_ldh_ac.v
Add cut 1 of a cellram module
[fpgaboy.git] / insn_ldh_ac.v
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CommitLineData
1`ifdef EXECUTE
2 `INSN_LDH_AC: begin
3 case (cycle)
4 0: if (opcode[4]) // LD A,(C)
5 `EXEC_READ(({8'hFF,`_C}))
6 else
7 `EXEC_WRITE(({8'hFF,`_C}), `_A)
8 1: begin
9 `EXEC_NEWCYCLE
10 `EXEC_INC_PC
11 end
12 endcase
13 end
14`endif
15
16`ifdef WRITEBACK
17 `INSN_LDH_AC: begin
18 case (cycle)
19 0: begin /* Type F */ end
20 1: if (opcode[4]) `_A <= rdata;
21 endcase
22 end
23`endif
24
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