]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - insn_ld_sp_hl.v
Add cut 1 of a cellram module
[fpgaboy.git] / insn_ld_sp_hl.v
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CommitLineData
1`ifdef EXECUTE
2 `INSN_LD_SP_HL: begin
3 case (cycle)
4 0: tmp <= `_H;
5 1: begin
6 `EXEC_NEWCYCLE
7 `EXEC_INC_PC
8 tmp <= `_L;
9 end
10 endcase
11 end
12`endif
13
14`ifdef WRITEBACK
15 `INSN_LD_SP_HL: begin
16 case (cycle)
17 0: `_SPH <= tmp;
18 1: `_SPL <= tmp;
19 endcase
20 end
21`endif
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