]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - rom.asm
Timer works.
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CommitLineData
1 SECTION "a",HOME
2
3main:
4 ld c, $51 ; Note that we are alive.
5 ld a, $FF
6 ld [c],a
7
8 ld sp, $DFFF
9
10 ld hl, signon
11 call puts
12
13 call memtest
14
15 call insntest
16
17 call waitsw
18
19 jr main
20
21signon:
22 db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
23
24; Memory tester: writes h ^ l to all addresses from C000 to DF80.
25memtest:
26 ld hl,memteststr
27 call puts
28
29 ld hl, $C000 ; Write loop
30.wr:
31 ld a,h
32 xor l
33 ld [hli],a
34 ld a, $DF
35 cp h
36 jr nz, .wr
37 ld a, $80
38 cp l
39 jr nz, .wr
40
41 ld hl, $C000 ; Read loop
42.rd:
43 ld a,h
44 xor l
45 ld b,a
46 ld a, [hli]
47 cp b
48 jr nz, .memfail
49
50 ld a, $DF
51 cp h
52 jr nz, .rd
53 ld a, $80
54 cp l
55 jr nz, .rd
56
57 ld hl, testokstr ; Say we're OK
58 call puts
59 ret
60.memfail: ; Say we failed (sadface)
61 ; decrement hl the easy way
62 ld a,[hld]
63 push hl
64 ld hl, failatstr
65 call puts
66 pop hl
67 ld a, h
68 call puthex
69 ld a, l
70 call puthex
71 ld a, $0A
72 call putc
73 ld a, $0D
74 call putc
75 ret
76memteststr:
77 db "Testing memory from $C000 to $DF80...",0
78testokstr:
79 db " OK!",$0D,$0A,0
80failatstr:
81 db " Test failed at $",0
82
83puthex: ; Put two hex nibbles to the serial console.
84 push af
85 rra
86 rra
87 rra
88 rra
89 ld b,$0F
90 and b
91 ld b,$30
92 add b
93 call putc
94 pop af
95 ld b,$0F
96 and b
97 ld b,$30
98 add b
99 call putc
100 ret
101
102; Wait for switches to be flipped on and off again.
103waitsw:
104 ld hl,waitswstr
105 call puts
106
107 ld c, $07
108 ld a, $04 ;start timer, 4.096KHz
109 ld [c], a
110
111 ld c, $51
112 ld a, $00
113 ld [c],a
114
115.loop1:
116 push bc
117 call testa
118 pop bc
119 ld c, $51
120 ld b, $0
121 ld a,[c]
122 cp b
123 jr z,.loop1
124.loop2:
125 ld a,[c]
126 cp b
127 jr nz,.loop2
128 ret
129
130waitswstr:
131 db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
132
133testa:
134 ld c, $0F
135 ld a, [c]
136 ld b, $00
137 cp b
138 ret z
139 xor a
140 ld [c], a
141 ld a, $41
142 call putc
143 ret
144
145; Core instruction basic acceptance tests.
146insntest:
147 ld hl, .insnteststr
148 call puts
149
150 ; Test PUSH and POP.
151 ld b, $12
152 ld c, $34
153 ld d, $56
154 ld e, $78
155 push bc
156 pop de
157 ld hl, .pushpopfail
158 ld a, d
159 cp b
160 jr nz,.fail
161 ld a, e
162 cp c
163 jr nz,.fail
164
165 ; Test ALU (HL).
166 ld hl, .ff
167 ld a, $FF
168 xor [hl]
169 ld hl, .xorhlfail
170 jr nz, .fail
171
172 ; Test JP (HL)
173 ld hl, .jphl
174 jp [hl]
175 ld hl, .jphlfail
176 jr .fail
177 rst $00
178.jphl:
179
180 ; Test JR
181 ld a, $FF
182 ld b, $00
183 cp b
184 jr nz,.jr
185 ld hl, .jrfail
186 jr .fail
187 rst $00
188.jr:
189
190 ; Test inc16
191 ld d, $12
192 ld e, $FF
193 ld hl, .inc16fail
194 inc de
195 ld a, $13
196 cp d
197 jr nz, .fail
198 ld a, $00
199 cp e
200 jr nz, .fail
201
202 ; Test CP.
203 ld hl, .cpfail
204 ld a, $10
205 ld b, $20
206 cp b
207 jr nc,.fail
208 ld a, $20
209 ld b, $10
210 cp b
211 jr c,.fail
212
213 ; Test CPL
214 ld hl, .cplfail
215 ld a, $55
216 ld b, $AA
217 cpl
218 cp b
219 jr nz,.fail
220
221 ld hl, .ok
222 call puts
223 ret
224.fail:
225 call puts
226 ld hl, .testfailed
227 call puts
228 ret
229.insnteststr:
230 db "Testing instructions... ",0
231.pushpopfail:
232 db "PUSH/POP",0
233.ff:
234 db $FF
235.xorhlfail:
236 db "XOR [HL]",0
237.jphlfail:
238 db "JP [HL]",0
239.jrfail:
240 db "JR",0
241.cpfail:
242 db "CP",0
243.cplfail:
244 db "CPL",0
245.inc16fail:
246 db "INC16",0
247.testfailed:
248 db " test failed.",$0D,$0A,0
249.ok:
250 db "OK!",$0D,$0A,0
251
252; Serial port manipulation functions.
253putc:
254 ld b, 0
255 ld c, $50
256 push af
257.waitport:
258 ld a,[c]
259 cp b
260 jr nz,.waitport
261 pop af
262 ld [c],a
263 ret
264
265puts:
266 ld a, [hli]
267 ld b, $00
268 cp b
269 jr z, .done
270 call putc
271 jr puts
272.done:
273 ret
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