Joshua Wise's Git repositories - fpgaboy.git/blame_incremental

... / ...

Commit	Line	Data
	1	VLOGS = 7seg.v Framebuffer.v core/GBZ80Core.v Interrupt.v LCDC.v Sound1.v \
	2	Sound2.v Soundcore.v System.v Timer.v Uart.v Buttons.v PS2Button.v
	3
	4	VLOGS_ALL = $(VLOGS) core/insn_call-callcc.v core/insn_incdec16.v \
	5	core/insn_jr-jrcc.v core/insn_ld_reg_hl.v core/insn_ld_reg_reg.v \
	6	core/insn_nop.v core/insn_ret-retcc.v core/allinsns.v \
	7	core/insn_alu8.v core/insn_di-ei.v core/insn_jp_hl.v \
	8	core/insn_ldh_ac.v core/insn_ld_reg_imm16.v core/insn_ld_sp_hl.v \
	9	core/insn_pop_reg.v core/insn_rst.v CPUDCM.v core/insn_alu_a.v \
	10	core/insn_halt.v core/insn_jp-jpcc.v core/insn_ld_hl_reg.v \
	11	core/insn_ld_reg_imm8.v core/insn_ldx_ahl.v core/insn_push_reg.v \
	12	core/insn_vop_intr.v core/insn_ldm8_a.v core/insn_ldm16_a.v \
	13	core/insn_ldbcde_a.v core/insn_alu_ext.v core/insn_bit.v \
	14	core/insn_two_byte.v core/insn_incdec_reg8.v core/insn_add_hl.v \
	15	core/insn_add_sp_imm8.v core/insn_ldhl_sp_imm8.v core/insn_ld_nn_sp.v
	16
	17	all: CoreTop.svf
	18
	19	sim: CoreTop_isim.exe
	20
	21	CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) fpgaboot.hex gbboot.hex
	22	xst -ifn CoreTop.xst -ofn CoreTop.syr
	23
	24	CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
	25	ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
	26
	27	CoreTop_map.ncd: CoreTop.ngd
	28	map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
	29
	30	CoreTop.ncd: CoreTop_map.ncd
	31	par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf
	32
	33	CoreTop.twr: CoreTop_map.ncd
	34	trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf
	35
	36	CoreTop.bit: CoreTop.ut CoreTop.ncd
	37	bitgen -f CoreTop.ut CoreTop.ncd
	38
	39	netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
	40	netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
	41
	42	netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
	43	vlogcomp netgen/par/CoreTop_timesim.v
	44	vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
	45
	46	CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
	47	fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
	48
	49	CoreTop_isim.exe: $(VLOGS_ALL)
	50	vlogcomp -d isim $(VLOGS)
	51	fuse -t CoreTop -o CoreTop_isim.exe
	52
	53	parsim: CoreTop_isim_par.exe
	54
	55	%.o: %.asm
	56	rgbasm -o$@ $<
	57
	58	%.bin: %.o
	59	echo "[Objects]" > tmp.lnk
	60	echo $< >> tmp.lnk
	61	echo "" >> tmp.lnk
	62	echo "[Output]" >> tmp.lnk
	63	echo $@ >> tmp.lnk
	64	xlink tmp.lnk
	65	rm tmp.lnk
	66
	67	%.mem: %.bin mashrom
	68	./mashrom < $< > $@
	69
	70	fpgaboot.hex: fpgaboot.bin mashrom
	71	./mashrom 256 < $< > $@
	72
	73
	74	CoreTop.svf: CoreTop.bit impact.cmd
	75	sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
	76	impact -batch tmp.cmd
	77
	78	parsim: CoreTop
	79