]> Joshua Wise's Git repositories - fpgaboy.git/blame_incremental - core/insn_push_reg.v
RAM needs to be writable, I guess
[fpgaboy.git] / core / insn_push_reg.v
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CommitLineData
1`define INSN_PUSH_reg 9'b011xx0101
2
3`ifdef EXECUTE
4 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
5 case (cycle)
6 0: case (opcode[5:4])
7 `INSN_stack_AF: `EXEC_WRITE(`_SP - 1, `_A)
8 `INSN_stack_BC: `EXEC_WRITE(`_SP - 1, `_B)
9 `INSN_stack_DE: `EXEC_WRITE(`_SP - 1, `_D)
10 `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_H)
11 endcase
12 1: case (opcode[5:4])
13 `INSN_stack_AF: `EXEC_WRITE(`_SP - 2, `_F)
14 `INSN_stack_BC: `EXEC_WRITE(`_SP - 2, `_C)
15 `INSN_stack_DE: `EXEC_WRITE(`_SP - 2, `_E)
16 `INSN_stack_HL: `EXEC_WRITE(`_SP - 2, `_L)
17 endcase
18 2: begin /* Twiddle thumbs. */ end
19 3: begin
20 `EXEC_NEWCYCLE
21 `EXEC_INC_PC
22 end
23 endcase
24 end
25`endif
26
27`ifdef WRITEBACK
28 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
29 case (cycle)
30 0: begin /* type F */ end
31 1: begin /* type F */ end
32 2: begin /* type F */ end
33 3: `_SP <= `_SP - 2;
34 endcase
35 end
36`endif
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