Joshua Wise's Git repositories - fpgaboy.git/blame_incremental

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Commit	Line	Data
	1	section "end",HOME[1024]
	2	nop
	3
	4	SECTION "a",HOME[$00]
	5
	6	start: jp main
	7
	8	section "vbl",HOME[$40]
	9	jp vbl
	10
	11	section "lcdc",HOME[$48]
	12	jp lcdc
	13
	14	section "tmro",HOME[$50]
	15	jp tmro
	16
	17	main:
	18	ld a, $FF
	19	ld c, $51
	20	ld [c], a
	21
	22	ld sp, $DFF0
	23
	24	ld a, $04 ;start timer, 4.096KHz
	25	ld c, $07
	26	ld [c], a
	27
	28	ld hl, $DF81
	29	xor a
	30	ld [hli], a
	31	ld [hli], a
	32
	33	ld hl, signon
	34	call puts
	35
	36	call putscreen
	37
	38	ei
	39
	40	call memtest
	41
	42	call insntest
	43
	44	call waitsw
	45
	46	di
	47
	48	jr main
	49
	50	signon:
	51	db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
	52
	53	putscreen:
	54	ld a, $FF ; Copy two tiles.
	55	ld hl, $8000
	56	ld [hli], a
	57	ld [hli], a
	58	xor a
	59	ld [hli], a
	60	ld [hli], a
	61
	62	ld hl, $9800
	63	.loop: ld a, $FF
	64	ld [hli], a
	65	xor a
	66	ld [hli], a
	67	ld a, h
	68	cp $9C
	69	jp nz,.loop
	70	ret
	71
	72	vbl:
	73	PUSH AF
	74	PUSH BC
	75	PUSH DE
	76	PUSH HL
	77
	78	xor a
	79	ld [$FF0F], a
	80
	81	ld c, $42 ; SCY
	82	ld a, [c]
	83	inc a
	84	ld [c], a
	85
	86	POP HL
	87	POP DE
	88	POP BC
	89	POP AF
	90
	91	RETI
	92
	93	lcdc:
	94	PUSH AF
	95	PUSH BC
	96
	97	xor a
	98	ld [$FF0F], a
	99
	100	POP BC
	101	POP AF
	102
	103	reti
	104
	105	tmro:
	106	PUSH AF
	107	PUSH BC
	108	PUSH DE
	109	PUSH HL
	110
	111	xor a
	112	ld [$FF0F], a
	113
	114	ld c, $45 ; LYC
	115	ld a, [c]
	116	inc a
	117	ld [c], a
	118
	119	ld a, [$DF82]
	120	cp 0
	121	jr z, .noprint
	122	ld a, $41 ; print A
	123	call putc
	124	.noprint:
	125	ld a, [$DF81]
	126	inc a
	127	ld [$DF81], a
	128	ld [$FF51], a
	129
	130	POP HL
	131	POP DE
	132	POP BC
	133	POP AF
	134	RETI
	135
	136	; Memory tester: writes h ^ l to all addresses from C000 to DF80.
	137	memtest:
	138	ld hl,memteststr
	139	call puts
	140
	141	ld hl, $C000 ; Write loop
	142	.wr:
	143	ld a,h
	144	xor l
	145	ld [hli],a
	146	ld a, h
	147	cp $DF
	148	jr nz, .wr
	149	ld a, l
	150	cp $80
	151	jr nz, .wr
	152
	153	ld hl, $C000 ; Read loop
	154	.rd:
	155	ld a,h
	156	xor l
	157	ld b,a
	158	ld a, [hli]
	159	cp b
	160	jr nz, .memfail
	161
	162	ld a, h
	163	cp $DF
	164	jr nz, .rd
	165	ld a, l
	166	cp $80
	167	jr nz, .rd
	168
	169	ld hl, testokstr ; Say we're OK
	170	call puts
	171	ret
	172	.memfail: ; Say we failed (sadface)
	173	; decrement hl the easy way
	174	dec [hl]
	175	push hl
	176	ld hl, failatstr
	177	call puts
	178	pop hl
	179	ld a, h
	180	call puthex
	181	ld a, l
	182	call puthex
	183	ld a, $0A
	184	call putc
	185	ld a, $0D
	186	call putc
	187	ret
	188	memteststr:
	189	db "Testing memory from $C000 to $DF80...",0
	190	testokstr:
	191	db " OK!",$0D,$0A,0
	192	failatstr:
	193	db " Test failed at $",0
	194
	195	puthex: ; Put two hex nibbles to the serial console.
	196	push af
	197	rra
	198	rra
	199	rra
	200	rra
	201	and $0F
	202	add $30
	203	call putc
	204	pop af
	205	and $0F
	206	add $30
	207	call putc
	208	ret
	209
	210	; Wait for switches to be flipped on and off again.
	211	waitsw:
	212	ld hl,waitswstr
	213	call puts
	214
	215	ld hl,$DF82
	216	ld a, 1
	217	ld [hl], a
	218
	219	ld c, $51
	220	xor a
	221	ld [c],a
	222
	223	.loop1:
	224	ld a,[c]
	225	cp $0
	226	jr z,.loop1
	227	.loop2:
	228	ld a,[c]
	229	cp $0
	230	jr nz,.loop2
	231	ret
	232
	233	waitswstr:
	234	db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
	235
	236	; Core instruction basic acceptance tests.
	237	insntest:
	238	ld hl, .insnteststr
	239	call puts
	240
	241	; Test PUSH and POP.
	242	ld b, $12
	243	ld c, $34
	244	ld d, $56
	245	ld e, $78
	246	push bc
	247	pop de
	248	ld hl, .pushpopfail
	249	ld a, d
	250	cp b
	251	jr nz,.fail
	252	ld a, e
	253	cp c
	254	jr nz,.fail
	255
	256	; Test ALU (HL).
	257	ld hl, .ff
	258	ld a, $FF
	259	xor [hl]
	260	ld hl, .xorhlfail
	261	jr nz, .fail
	262
	263	; Test JP (HL)
	264	ld hl, .jphl
	265	jp [hl]
	266	ld hl, .jphlfail
	267	jr .fail
	268	rst $00
	269	.jphl:
	270
	271	; Test JR
	272	ld a, $FF
	273	cp $0
	274	jr nz,.jr
	275	ld hl, .jrfail
	276	jr .fail
	277	rst $00
	278	.jr:
	279
	280	; Test inc16
	281	ld d, $12
	282	ld e, $FF
	283	ld hl, .inc16fail
	284	inc de
	285	ld a, $13
	286	cp d
	287	jr nz, .fail
	288	ld a, $00
	289	cp e
	290	jr nz, .fail
	291
	292	; Test CP.
	293	ld hl, .cpfail
	294	ld a, $10
	295	cp $20
	296	jr nc,.fail
	297	ld a, $20
	298	cp $10
	299	jr c,.fail
	300
	301	; Test CPL
	302	ld hl, .cplfail
	303	ld a, $55
	304	cpl
	305	cp $AA
	306	jr nz,.fail
	307
	308	; Test DI/EI delay
	309	di
	310	ld hl, .dinocausefail
	311	ld c, $0F ; First, wait until an interrupt happens...
	312	.wait: ld a, [c]
	313	and $04
	314	cp 0
	315	jr z, .wait
	316	ei ; Now make sure that an IRQ didn't happen on EI/DI
	317	di
	318	ld a, [c]
	319	and $04
	320	cp 0
	321	jr z, .fail
	322	ld hl, .dicausefail
	323	ei ; Make sure that an IRQ does happen on EI/NOP/DI
	324	nop
	325	nop
	326	di
	327	ld a, [c]
	328	and $04
	329	cp 0
	330	jr nz, .fail
	331	ei
	332
	333	ld hl, .ok
	334	call puts
	335	ret
	336	.fail:
	337	ei
	338	call puts
	339	ld hl, .testfailed
	340	call puts
	341	ret
	342	.insnteststr:
	343	db "Testing instructions... ",0
	344	.pushpopfail:
	345	db "PUSH/POP",0
	346	.ff:
	347	db $FF
	348	.xorhlfail:
	349	db "XOR [HL]",0
	350	.jphlfail:
	351	db "JP [HL]",0
	352	.jrfail:
	353	db "JR",0
	354	.cpfail:
	355	db "CP",0
	356	.cplfail:
	357	db "CPL",0
	358	.inc16fail:
	359	db "INC16",0
	360	.dinocausefail:
	361	db "DI/EI does not cause interrupt",0
	362	.dicausefail:
	363	db "DI/NOP/EI cause interrupt",0
	364	.testfailed:
	365	db " test failed.",$0D,$0A,0
	366	.ok:
	367	db "OK!",$0D,$0A,0
	368
	369	; Serial port manipulation functions.
	370	putc:
	371	ld c, $50
	372	push af
	373	.waitport:
	374	ld a,[c]
	375	cp $00
	376	jr nz,.waitport
	377	pop af
	378	ld [c],a
	379	ret
	380
	381	puts:
	382	ld a, [hli]
	383	cp $00
	384	ret z
	385	call putc
	386	jr puts
	387