]>
Commit | Line | Data |
---|---|---|
1 | `define ADDR_IF 16'hFF0F | |
2 | `define ADDR_IE 16'hFFFF | |
3 | ||
4 | module Interrupt( | |
5 | input clk, | |
6 | input rd, | |
7 | input wr, | |
8 | input [15:0] addr, | |
9 | inout [7:0] data, | |
10 | input vblank, | |
11 | input lcdc, | |
12 | input tovf, | |
13 | input serial, | |
14 | input buttons, | |
15 | output master, | |
16 | input ack, | |
17 | output [7:0] jaddr); | |
18 | ||
19 | wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank}; | |
20 | reg [7:0] imask = 16'hFFFF; | |
21 | reg [7:0] ihold = 8'b0; | |
22 | wire [7:0] imasked = ihold & imask; | |
23 | ||
24 | reg rdlatch = 0; | |
25 | reg [15:0] addrlatch = 0; | |
26 | ||
27 | assign data = rdlatch ? | |
28 | (addrlatch == `ADDR_IF) ? ihold : | |
29 | (addrlatch == `ADDR_IE) ? imask : | |
30 | 8'bzzzzzzzz : | |
31 | 8'bzzzzzzzz; | |
32 | ||
33 | assign master = (imasked) != 0; | |
34 | ||
35 | assign jaddr = imasked[0] ? 8'h40 : | |
36 | imasked[1] ? 8'h48 : | |
37 | imasked[2] ? 8'h50 : | |
38 | imasked[3] ? 8'h58 : | |
39 | imasked[4] ? 8'h60 : 8'h00; | |
40 | ||
41 | always @(posedge clk) | |
42 | begin | |
43 | if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin | |
44 | case(addr) | |
45 | `ADDR_IF : ihold <= iflag | data; | |
46 | `ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end | |
47 | endcase | |
48 | ||
49 | end else if (ack) | |
50 | ihold <= ihold & | |
51 | (imasked[0] ? 8'b11111110 : | |
52 | imasked[1] ? 8'b11111101 : | |
53 | imasked[2] ? 8'b11111011 : | |
54 | imasked[3] ? 8'b11110111 : | |
55 | imasked[4] ? 8'b11101111 : | |
56 | 8'b11111111); | |
57 | else | |
58 | ihold <= ihold | iflag; | |
59 | rdlatch <= rd; | |
60 | addrlatch <= addr; | |
61 | end | |
62 | ||
63 | endmodule |