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1 | `define ADDR_IF 16'hFF0F | |
2 | `define ADDR_IE 16'hFFFF | |
3 | ||
4 | module Interrupt( | |
5 | input clk, | |
6 | input rd, | |
7 | input wr, | |
8 | input [15:0] addr, | |
9 | inout [7:0] data, | |
10 | input vblank, | |
11 | input lcdc, | |
12 | input tovf, | |
13 | input serial, | |
14 | input buttons, | |
15 | output master, | |
16 | output [7:0] jaddr); | |
17 | ||
18 | wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank}; | |
19 | reg [7:0] imask = 16'hFFFF; | |
20 | reg [7:0] ihold = 0; | |
21 | wire [7:0] imasked = ihold & imask; | |
22 | ||
23 | assign data = rd ? | |
24 | (addr == `ADDR_IF) ? ihold : | |
25 | (addr == `ADDR_IE) ? imask : | |
26 | 8'bzzzzzzzz : | |
27 | 8'bzzzzzzzz; | |
28 | ||
29 | assign master = (imasked) != 0; | |
30 | ||
31 | assign jaddr = imasked[0] ? 8'h40 : | |
32 | imasked[1] ? 8'h48 : | |
33 | imasked[2] ? 8'h50 : | |
34 | imasked[3] ? 8'h58 : | |
35 | imasked[4] ? 8'h60 : 8'h00; | |
36 | ||
37 | always @ (negedge clk) | |
38 | begin | |
39 | if (wr) begin | |
40 | case(addr) | |
41 | `ADDR_IF : ihold <= iflag | data; | |
42 | `ADDR_IE : imask <= data; | |
43 | endcase | |
44 | ||
45 | end | |
46 | else | |
47 | ihold <= ihold | iflag; | |
48 | end | |
49 | ||
50 | endmodule |