Joshua Wise's Git repositories - fpgaboy.git/blame_incremental

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Commit	Line	Data
	1	YET UNIMPLEMENTED:
	2
	3	imm3 = 3-bit immediate value in 8 bits
	4	imm8 = 8-bit immediate value
	5	imm16 = 16-bit immediate value
	6	16m8 = 8-bit value at the 16-bit address
	7	8m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
	8
	9	bits insn notes
	10	0000 0010 LD (BC), A
	11	0000 1000 LD 16m16,SP loads SP
	12	0000 1001 ADD HL, BC
	13	0000 1010 LD A, (BC)
	14	0001 0000 STOP
	15	0001 0010 LD (DE), A
	16	0001 1001 ADD HL, DE
	17	0001 1010 LD A, (DE)
	18	0010 1001 ADD HL, HL
	19	0011 1001 ADD HL, SP
	20	0111 0110 HALT Danger! Helvetica!
	21	1100 1011 - - - see two-byte opcodes below
	22	1110 1000 ADD SP, imm8
	23	1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL
	24
	25	*****************************
	26
	27	fucking two-byte opcodes
	28
	29	bits insn notes
	30	1100 1011 0000 0000 RLC B
	31	1100 1011 0000 0001 RLC C
	32	1100 1011 0000 0010 RLC D
	33	1100 1011 0000 0011 RLC E
	34	1100 1011 0000 0100 RLC H
	35	1100 1011 0000 0101 RLC L
	36	1100 1011 0000 0110 RLC (HL)
	37	1100 1011 0000 0111 RLC A
	38
	39	1100 1011 0000 1000 RRC B
	40	1100 1011 0000 1001 RRC C
	41	1100 1011 0000 1010 RRC D
	42	1100 1011 0000 1011 RRC E
	43	1100 1011 0000 1100 RRC H
	44	1100 1011 0000 1101 RRC L
	45	1100 1011 0000 1110 RRC (HL)
	46	1100 1011 0000 1111 RRC A
	47
	48	1100 1011 0001 0000 RL B
	49	1100 1011 0001 0001 RL C
	50	1100 1011 0001 0010 RL D
	51	1100 1011 0001 0011 RL E
	52	1100 1011 0001 0100 RL H
	53	1100 1011 0001 0101 RL L
	54	1100 1011 0001 0110 RL (HL)
	55	1100 1011 0001 0111 RL A
	56
	57	1100 1011 0001 1000 RR B
	58	1100 1011 0001 1001 RR C
	59	1100 1011 0001 1010 RR D
	60	1100 1011 0001 1011 RR E
	61	1100 1011 0001 1100 RR H
	62	1100 1011 0001 1101 RR L
	63	1100 1011 0001 1110 RR (HL)
	64	1100 1011 0001 1111 RR A
	65
	66	1100 1011 0010 0000 SLA B
	67	1100 1011 0010 0001 SLA C
	68	1100 1011 0010 0010 SLA D
	69	1100 1011 0010 0011 SLA E
	70	1100 1011 0010 0100 SLA H
	71	1100 1011 0010 0101 SLA L
	72	1100 1011 0010 0110 SLA (HL)
	73	1100 1011 0010 0111 SLA A
	74
	75	1100 1011 0010 1000 SRA B
	76	1100 1011 0010 1001 SRA C
	77	1100 1011 0010 1010 SRA D
	78	1100 1011 0010 1011 SRA E
	79	1100 1011 0010 1100 SRA H
	80	1100 1011 0010 1101 SRA L
	81	1100 1011 0010 1110 SRA (HL)
	82	1100 1011 0010 1111 SRA A
	83
	84	1100 1011 0011 1000 SRL B
	85	1100 1011 0011 1001 SRL C
	86	1100 1011 0011 1010 SRL D
	87	1100 1011 0011 1011 SRL E
	88	1100 1011 0011 1100 SRL H
	89	1100 1011 0011 1101 SRL L
	90	1100 1011 0011 1110 SRL (HL)
	91	1100 1011 0011 1111 SRL A
	92
	93	1100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte
	94	1100 1011 0011 0001 SWAP C
	95	1100 1011 0011 0010 SWAP D
	96	1100 1011 0011 0011 SWAP E
	97	1100 1011 0011 0100 SWAP H
	98	1100 1011 0011 0101 SWAP L
	99	1100 1011 0011 0110 SWAP (HL)
	100	1100 1011 0011 0111 SWAP A
	101
	102	1100 1011 0100 0000 BIT imm3, B test bit specified by imm3
	103	1100 1011 0100 0001 BIT imm3, C
	104	1100 1011 0100 0010 BIT imm3, D
	105	1100 1011 0100 0011 BIT imm3, E
	106	1100 1011 0100 0100 BIT imm3, H
	107	1100 1011 0100 0101 BIT imm3, L
	108	1100 1011 0100 0110 BIT imm3, (HL)
	109	1100 1011 0100 0111 BIT imm3, A
	110
	111	1100 1011 1000 0000 RES imm3, B reset bit specified by imm3
	112	1100 1011 1000 0001 RES imm3, C
	113	1100 1011 1000 0010 RES imm3, D
	114	1100 1011 1000 0011 RES imm3, E
	115	1100 1011 1000 0100 RES imm3, H
	116	1100 1011 1000 0101 RES imm3, L
	117	1100 1011 1000 0110 RES imm3, (HL)
	118	1100 1011 1000 0111 RES imm3, A
	119
	120	1100 1011 1100 0000 SET imm3, B set bit specified by imm3
	121	1100 1011 1100 0001 SET imm3, C
	122	1100 1011 1100 0010 SET imm3, D
	123	1100 1011 1100 0011 SET imm3, E
	124	1100 1011 1100 0100 SET imm3, H
	125	1100 1011 1100 0101 SET imm3, L
	126	1100 1011 1100 0110 SET imm3, (HL)
	127	1100 1011 1100 0111 SET imm3, A