Joshua Wise's Git repositories - fpgaboy.git/blame_incremental

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Commit	Line	Data
	1	YET UNIMPLEMENTED:
	2
	3	imm3 = 3-bit immediate value in 8 bits
	4	imm8 = 8-bit immediate value
	5	imm16 = 16-bit immediate value
	6	16m8 = 8-bit value at the 16-bit address
	7	8m8 = 8-bit value at the 8-bit address (the 16-bit equivalent is 0xFF00 + addr)
	8
	9	bits insn notes
	10	0000 1000 LD 16m16,SP loads SP
	11	0001 0000 STOP
	12	0111 0110 HALT Danger! Helvetica!
	13	1100 1011 - - - see two-byte opcodes below
	14	1110 1000 ADD SP, imm8
	15	1111 1000 LDHL SP, imm8 load SP+n (signed n) into HL
	16
	17	*****************************
	18
	19	fucking two-byte opcodes
	20
	21	bits insn notes
	22	1100 1011 0000 0000 RLC B
	23	1100 1011 0000 0001 RLC C
	24	1100 1011 0000 0010 RLC D
	25	1100 1011 0000 0011 RLC E
	26	1100 1011 0000 0100 RLC H
	27	1100 1011 0000 0101 RLC L
	28	1100 1011 0000 0110 RLC (HL)
	29	1100 1011 0000 0111 RLC A
	30
	31	1100 1011 0000 1000 RRC B
	32	1100 1011 0000 1001 RRC C
	33	1100 1011 0000 1010 RRC D
	34	1100 1011 0000 1011 RRC E
	35	1100 1011 0000 1100 RRC H
	36	1100 1011 0000 1101 RRC L
	37	1100 1011 0000 1110 RRC (HL)
	38	1100 1011 0000 1111 RRC A
	39
	40	1100 1011 0001 0000 RL B
	41	1100 1011 0001 0001 RL C
	42	1100 1011 0001 0010 RL D
	43	1100 1011 0001 0011 RL E
	44	1100 1011 0001 0100 RL H
	45	1100 1011 0001 0101 RL L
	46	1100 1011 0001 0110 RL (HL)
	47	1100 1011 0001 0111 RL A
	48
	49	1100 1011 0001 1000 RR B
	50	1100 1011 0001 1001 RR C
	51	1100 1011 0001 1010 RR D
	52	1100 1011 0001 1011 RR E
	53	1100 1011 0001 1100 RR H
	54	1100 1011 0001 1101 RR L
	55	1100 1011 0001 1110 RR (HL)
	56	1100 1011 0001 1111 RR A
	57
	58	1100 1011 0010 0000 SLA B
	59	1100 1011 0010 0001 SLA C
	60	1100 1011 0010 0010 SLA D
	61	1100 1011 0010 0011 SLA E
	62	1100 1011 0010 0100 SLA H
	63	1100 1011 0010 0101 SLA L
	64	1100 1011 0010 0110 SLA (HL)
	65	1100 1011 0010 0111 SLA A
	66
	67	1100 1011 0010 1000 SRA B
	68	1100 1011 0010 1001 SRA C
	69	1100 1011 0010 1010 SRA D
	70	1100 1011 0010 1011 SRA E
	71	1100 1011 0010 1100 SRA H
	72	1100 1011 0010 1101 SRA L
	73	1100 1011 0010 1110 SRA (HL)
	74	1100 1011 0010 1111 SRA A
	75
	76	1100 1011 0011 1000 SRL B
	77	1100 1011 0011 1001 SRL C
	78	1100 1011 0011 1010 SRL D
	79	1100 1011 0011 1011 SRL E
	80	1100 1011 0011 1100 SRL H
	81	1100 1011 0011 1101 SRL L
	82	1100 1011 0011 1110 SRL (HL)
	83	1100 1011 0011 1111 SRL A
	84
	85	1100 1011 0011 0000 SWAP B swaps upper and lower nibbles of a byte
	86	1100 1011 0011 0001 SWAP C
	87	1100 1011 0011 0010 SWAP D
	88	1100 1011 0011 0011 SWAP E
	89	1100 1011 0011 0100 SWAP H
	90	1100 1011 0011 0101 SWAP L
	91	1100 1011 0011 0110 SWAP (HL)
	92	1100 1011 0011 0111 SWAP A
	93
	94	1100 1011 1000 0000 RES imm3, B reset bit specified by imm3
	95	1100 1011 1000 0001 RES imm3, C
	96	1100 1011 1000 0010 RES imm3, D
	97	1100 1011 1000 0011 RES imm3, E
	98	1100 1011 1000 0100 RES imm3, H
	99	1100 1011 1000 0101 RES imm3, L
	100	1100 1011 1000 0110 RES imm3, (HL)
	101	1100 1011 1000 0111 RES imm3, A
	102
	103	1100 1011 1100 0000 SET imm3, B set bit specified by imm3
	104	1100 1011 1100 0001 SET imm3, C
	105	1100 1011 1100 0010 SET imm3, D
	106	1100 1011 1100 0011 SET imm3, E
	107	1100 1011 1100 0100 SET imm3, H
	108	1100 1011 1100 0101 SET imm3, L
	109	1100 1011 1100 0110 SET imm3, (HL)
	110	1100 1011 1100 0111 SET imm3, A