git.joshuawise.com / fpgaboy.git / blame
| Commit | Line | Data |
|---|---|---|
| 5bac4cf0 JW |
1 | VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \ |
| 2 | insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \ | |
| 3 | insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \ | |
| 4 | insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \ | |
| 5 | insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \ | |
| 6 | insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \ | |
| 7 | insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \ | |
| 8 | Timer.v | |
| 9c834ff2 | 9 | |
| 5bac4cf0 | 10 | all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr |
| 9c834ff2 | 11 | |
| 6c46357c | 12 | CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) |
| 9c834ff2 JW |
13 | xst -ifn CoreTop.xst -ofn CoreTop.syr |
| 14 | ||
| 5bac4cf0 JW |
15 | CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf |
| 16 | ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd | |
| 9c834ff2 JW |
17 | |
| 18 | CoreTop_map.ncd: CoreTop.ngd | |
| 19 | map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf | |
| 20 | ||
| 21 | CoreTop.ncd: CoreTop_map.ncd | |
| 22 | par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf | |
| 23 | ||
| 24 | CoreTop.twr: CoreTop_map.ncd | |
| 25 | trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf | |
| 26 | ||
| 27 | CoreTop.bit: CoreTop.ut CoreTop.ncd | |
| 28 | bitgen -f CoreTop.ut CoreTop.ncd | |
| 7028b02c | 29 | |
| 179b4347 JW |
30 | netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd |
| 31 | netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v | |
| 32 | ||
| 33 | netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v | |
| 34 | vlogcomp netgen/par/CoreTop_timesim.v | |
| 35 | vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v | |
| 36 | ||
| 37 | CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work | |
| 38 | fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl | |
| 39 | ||
| 40 | parsim: CoreTop_isim_par.exe | |
| 41 | ||
| 5bac4cf0 JW |
42 | %.o: %.asm |
| 43 | rgbasm -o$@ $< | |
| 7028b02c | 44 | |
| 5bac4cf0 JW |
45 | %.bin: %.o rom.lnk |
| 46 | echo "[Objects]" > tmp.lnk | |
| 47 | echo $< >> tmp.lnk | |
| 48 | echo "" >> tmp.lnk | |
| 49 | echo "[Output]" >> tmp.lnk | |
| 50 | echo $@ >> tmp.lnk | |
| 51 | xlink tmp.lnk | |
| 52 | rm tmp.lnk | |
| 7028b02c | 53 | |
| 5bac4cf0 JW |
54 | %.mem: %.bin |
| 55 | ./mashrom < $< > $@ | |
| 7028b02c | 56 | |
| 5bac4cf0 JW |
57 | CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm |
| 58 | data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@ | |
| 7028b02c | 59 | |
| 5bac4cf0 JW |
60 | CoreTop_%.svf: CoreTop_%.bit impact.cmd |
| 61 | sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd | |
| 62 | impact -batch tmp.cmd | |
| 179b4347 JW |
63 | |
| 64 | parsim: CoreTop | |
| 65 |