Add DI/EI delay test. Add LD M, A.
[fpgaboy.git] / GBZ80Core.v
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1`define REG_A 0
2`define REG_B 1
3`define REG_C 2
4`define REG_D 3
5`define REG_E 4
6`define REG_F 5
7`define REG_H 6
8`define REG_L 7
9`define REG_SPH 8
10`define REG_SPL 9
11`define REG_PCH 10
12`define REG_PCL 11
2f55f809 13
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14`define _A registers[`REG_A]
15`define _B registers[`REG_B]
16`define _C registers[`REG_C]
17`define _D registers[`REG_D]
18`define _E registers[`REG_E]
19`define _F registers[`REG_F]
20`define _H registers[`REG_H]
21`define _L registers[`REG_L]
22`define _SPH registers[`REG_SPH]
23`define _SPL registers[`REG_SPL]
24`define _PCH registers[`REG_PCH]
25`define _PCL registers[`REG_PCL]
26`define _AF {`_A, `_F}
27`define _BC {`_B, `_C}
28`define _DE {`_D, `_E}
29`define _HL {`_H, `_L}
30`define _SP {`_SPH, `_SPL}
31`define _PC {`_PCH, `_PCL}
32
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33`define FLAG_Z 8'b10000000
34`define FLAG_N 8'b01000000
35`define FLAG_H 8'b00100000
36`define FLAG_C 8'b00010000
2f55f809 37
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38`define STATE_FETCH 2'h0
39`define STATE_DECODE 2'h1
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40`define STATE_EXECUTE 2'h2
41`define STATE_WRITEBACK 2'h3
42
43`define INSN_LD_reg_imm8 8'b00xxx110
df770340 44`define INSN_HALT 8'b01110110
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45`define INSN_LD_HL_reg 8'b01110xxx
46`define INSN_LD_reg_HL 8'b01xxx110
47`define INSN_LD_reg_reg 8'b01xxxxxx
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48`define INSN_LD_reg_imm16 8'b00xx0001
49`define INSN_LD_SP_HL 8'b11111001
97649fed 50`define INSN_PUSH_reg 8'b11xx0101
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51`define INSN_POP_reg 8'b11xx0001
52`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
53`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
54`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
f888201b 55`define INSN_ALU8IMM 8'b11xxx110
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56`define INSN_NOP 8'b00000000
57`define INSN_RST 8'b11xxx111
58`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
59`define INSN_RETCC 8'b110xx000
60`define INSN_CALL 8'b11001101
61`define INSN_CALLCC 8'b110xx100 // Not that call/cc.
62`define INSN_JP_imm 8'b11000011
a85b19a7 63`define INSN_JPCC_imm 8'b110xx010
a00483d0 64`define INSN_ALU_A 8'b00xxx111
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65`define INSN_JP_HL 8'b11101001
66`define INSN_JR_imm 8'b00011000
722e486a 67`define INSN_JRCC_imm 8'b001xx000
dadf7990 68`define INSN_INCDEC16 8'b00xxx011
f8db6448 69`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
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70`define INSN_DI 8'b11110011
71`define INSN_EI 8'b11111011
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72`define INSN_INCDEC_HL 8'b0011010x
73`define INSN_INCDEC_reg8 8'b00xxx10x
f9000d73 74`define INSN_LDM_A 8'b111xx000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
a85b19a7 75
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76`define INSN_cc_NZ 2'b00
77`define INSN_cc_Z 2'b01
78`define INSN_cc_NC 2'b10
79`define INSN_cc_C 2'b11
fa136d63 80
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81`define INSN_reg_A 3'b111
82`define INSN_reg_B 3'b000
83`define INSN_reg_C 3'b001
84`define INSN_reg_D 3'b010
85`define INSN_reg_E 3'b011
86`define INSN_reg_H 3'b100
87`define INSN_reg_L 3'b101
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88`define INSN_reg_dHL 3'b110
89`define INSN_reg16_BC 2'b00
90`define INSN_reg16_DE 2'b01
91`define INSN_reg16_HL 2'b10
92`define INSN_reg16_SP 2'b11
93`define INSN_stack_AF 2'b11
94`define INSN_stack_BC 2'b00
95`define INSN_stack_DE 2'b01
96`define INSN_stack_HL 2'b10
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97`define INSN_alu_ADD 3'b000
98`define INSN_alu_ADC 3'b001
99`define INSN_alu_SUB 3'b010
100`define INSN_alu_SBC 3'b011
101`define INSN_alu_AND 3'b100
102`define INSN_alu_XOR 3'b101
103`define INSN_alu_OR 3'b110
104`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
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105`define INSN_alu_RLCA 3'b000
106`define INSN_alu_RRCA 3'b001
107`define INSN_alu_RLA 3'b010
108`define INSN_alu_RRA 3'b011
109`define INSN_alu_DAA 3'b100
110`define INSN_alu_CPL 3'b101
111`define INSN_alu_SCF 3'b110
112`define INSN_alu_CCF 3'b111
94522011 113
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114`define EXEC_INC_PC `_PC <= `_PC + 1;
115`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
116`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
117`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
118`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
5509558d 119
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120module GBZ80Core(
121 input clk,
eb0f2fe1 122 output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
2f55f809 123 inout [7:0] busdata,
eb0f2fe1 124 output reg buswr, output reg busrd,
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125 input irq, input [7:0] jaddr,
126 output reg [1:0] state);
2f55f809 127
6c46357c 128// reg [1:0] state; /* State within this bus cycle (see STATE_*). */
9c834ff2 129 reg [2:0] cycle; /* Cycle for instructions. */
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130
131 reg [7:0] registers[11:0];
132
133 reg [15:0] address; /* Address for the next bus operation. */
134
135 reg [7:0] opcode; /* Opcode from the current machine cycle. */
136
137 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
9c834ff2 138 reg rd, wr, newcycle;
2f55f809 139
ef6fbe31 140 reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0 141
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142 reg [7:0] buswdata;
143 assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
144
eb0f2fe1 145 reg ie, iedelay;
abae5818 146
2f55f809 147 initial begin
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148 registers[ 0] <= 0;
149 registers[ 1] <= 0;
150 registers[ 2] <= 0;
151 registers[ 3] <= 0;
152 registers[ 4] <= 0;
153 registers[ 5] <= 0;
154 registers[ 6] <= 0;
155 registers[ 7] <= 0;
156 registers[ 8] <= 0;
157 registers[ 9] <= 0;
158 registers[10] <= 0;
159 registers[11] <= 0;
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160 rd <= 1;
161 wr <= 0;
162 newcycle <= 1;
163 state <= 0;
164 cycle <= 0;
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165 busrd <= 0;
166 buswr <= 0;
167 busaddress <= 0;
9c834ff2 168 ie <= 0;
f8db6448 169 iedelay <= 0;
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170 opcode <= 0;
171 state <= `STATE_WRITEBACK;
172 cycle <= 0;
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173 end
174
175 always @(posedge clk)
176 case (state)
177 `STATE_FETCH: begin
2e642f1f 178 if (newcycle) begin
2f55f809 179 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
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180 buswr <= 0;
181 busrd <= 1;
182 end else begin
2f55f809 183 busaddress <= address;
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184 buswr <= wr;
185 busrd <= rd;
186 if (wr)
187 buswdata <= wdata;
188 end
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189 state <= `STATE_DECODE;
190 end
191 `STATE_DECODE: begin
192 if (newcycle) begin
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193 if (ie && irq)
194 opcode <= `INSN_VOP_INTR;
195 else
196 opcode <= busdata;
2f55f809 197 rdata <= busdata;
b85870e0 198 newcycle <= 0;
2f55f809 199 cycle <= 0;
2e642f1f 200 end else begin
2f55f809 201 if (rd) rdata <= busdata;
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202 cycle <= cycle + 1;
203 end
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204 if (iedelay) begin
205 ie <= 1;
206 iedelay <= 0;
207 end
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208 buswr <= 0;
209 busrd <= 0;
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210 wr <= 0;
211 rd <= 0;
212 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
213 wdata <= 8'bxxxxxxxx;
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214 state <= `STATE_EXECUTE;
215 end
216 `STATE_EXECUTE: begin
2f55f809 217 casex (opcode)
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218 `define EXECUTE
219 `include "allinsns.v"
220 `undef EXECUTE
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221 default:
222 $stop;
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223 endcase
224 state <= `STATE_WRITEBACK;
225 end
226 `STATE_WRITEBACK: begin
227 casex (opcode)
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228 `define WRITEBACK
229 `include "allinsns.v"
230 `undef WRITEBACK
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231 default:
232 $stop;
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233 endcase
234 state <= `STATE_FETCH;
235 end
236 endcase
237endmodule
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