[fpgaboy.git] / insn_ld_reg_hl.v

`ifdef EXECUTE
	`INSN_LD_reg_HL: begin
		case(cycle)
		0:	`EXEC_READ(`_HL)
		1:	begin
				`EXEC_INC_PC
				`EXEC_NEWCYCLE
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_HL: begin
		case (cycle)
		0:	begin end
		1:	case (opcode[5:3])
			`INSN_reg_A:	`_A <= rdata;
			`INSN_reg_B:	`_B <= rdata;
			`INSN_reg_C:	`_C <= rdata;
			`INSN_reg_D:	`_D <= rdata;
			`INSN_reg_E:	`_E <= rdata;
			`INSN_reg_H:	`_H <= rdata;
			`INSN_reg_L:	`_L <= rdata;
			endcase
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_reg_HL: begin
	3	case(cycle)
5c33c5c0	4	0: `EXEC_READ(`_HL)
81358c71	5	1: begin
5c33c5c0 JW	6	`EXEC_INC_PC
5c33c5c0 JW	7	`EXEC_NEWCYCLE
81358c71 JW	8	end
	9	endcase
	10	end
	11	`endif
	12
	13	`ifdef WRITEBACK
	14	`INSN_LD_reg_HL: begin
	15	case (cycle)
	16	0: begin end
5c33c5c0 JW	17	1: case (opcode[5:3])
	18	`INSN_reg_A: `_A <= rdata;
	19	`INSN_reg_B: `_B <= rdata;
	20	`INSN_reg_C: `_C <= rdata;
	21	`INSN_reg_D: `_D <= rdata;
	22	`INSN_reg_E: `_E <= rdata;
	23	`INSN_reg_H: `_H <= rdata;
	24	`INSN_reg_L: `_L <= rdata;
	25	endcase
81358c71 JW	26	endcase
	27	end
	28	`endif