]> Joshua Wise's Git repositories - fpgaboy.git/blame - rom.asm
Add some verilator and isim compatibility
[fpgaboy.git] / rom.asm
CommitLineData
616eebe0 1 SECTION "a",HOME
20204e79 2
616eebe0 3main:
00573fd5
JW
4 ld a, $FF ; Note that we are alive.
5 ld [$FF51],a
62940da0 6
9c834ff2
JW
7 ld sp, $DFF0
8
30ef1ae0
JW
9 ld hl, $DF81
10 ld a, $80
11 ld [hl], a
9c834ff2 12
30ef1ae0
JW
13 ld c, $07
14 ld a, $04 ;start timer, 4.096KHz
15 ld [c], a
5bac4cf0
JW
16;diqs: ei
17; ld a, $80
18; ld c, $51
19; ld [c], a
20; jr diqs
21 call irqhand
30ef1ae0 22 ei
5bac4cf0 23coqs: jr coqs
20204e79 24
5bac4cf0
JW
25 section "Diq", HOME[$38]
26fuqed:
31833112 27 di
5bac4cf0 28 jr fuqed
20204e79 29
5bac4cf0 30 section "fuq",HOME[$100]
31833112
JW
31irqhand:
32 PUSH AF
33 PUSH BC
34 PUSH DE
35 PUSH HL
9c834ff2 36
31833112
JW
37 xor a
38 ld c, $0F ; ack the irq
39 ld [c], a
9c834ff2 40
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JW
41 ld a, $41 ; print A
42 call putc
9c834ff2 43
30ef1ae0 44 ld hl, $DF81
f9000d73 45 inc [hl]
30ef1ae0 46 ld a, [hl]
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JW
47 ld c, $51
48 ld [c], a
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49
50
31833112
JW
51 POP HL
52 POP DE
53 POP BC
54 POP AF
55 RETI
5bac4cf0
JW
56 db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
57 db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
58 db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
30ef1ae0
JW
59
60putc:
61 ld b, 0
62 ld c, $50
63 push af
64.waitport:
65 ld a,[c]
66 cp b
67 jr nz,.waitport
68 pop af
69 ld [c],a
70 ret
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