Set up the bus a little before the clock.

[fpgaboy.git] / insn_incdec_reg8.v

`ifdef EXECUTE
	`INSN_INCDEC_reg8: begin
		`EXEC_INC_PC
		`EXEC_NEWCYCLE
		case (opcode[5:3])
		`INSN_reg_A:	tmp <= `_A;
		`INSN_reg_B:	tmp <= `_B;
		`INSN_reg_C:	tmp <= `_C;
		`INSN_reg_D:	tmp <= `_D;
		`INSN_reg_E:	tmp <= `_E;
		`INSN_reg_H:	tmp <= `_H;
		`INSN_reg_L:	tmp <= `_L;
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_INCDEC_reg8: begin
		case (opcode[5:3])
		`INSN_reg_A:	`_A <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_B:	`_B <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_C:	`_C <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_D:	`_D <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_E:	`_E <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_H:	`_H <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		`INSN_reg_L:	`_L <= tmp + (opcode[0] ? 8'hFF : 8'h01);
		endcase
		`_F <= {
				(tmp + (opcode[0] ? 8'hFF : 8'h01)) ? 1'b0 : 1'b1,
				1'b0,
				(({1'b0,tmp[3:0]} + (opcode[0] ? 5'h1F : 5'h01)) >> 4) ? 1'b1 : 1'b0,
				`_F[4:0]};
	end
`endif