Move the core to core/

[fpgaboy.git] / core / insn_jr-jrcc.v

`ifdef EXECUTE
	`INSN_JR_imm,`INSN_JRCC_imm: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 1)
			end
		1: 	begin
				`EXEC_INC_PC
				if (opcode[5]) begin	// i.e., JP cc,nn
					/* We need to check the condition code to bail out. */
					case (opcode[4:3])
					`INSN_cc_NZ:	if (`_F[7]) `EXEC_NEWCYCLE
					`INSN_cc_Z:	if (~`_F[7]) `EXEC_NEWCYCLE
					`INSN_cc_NC:	if (`_F[4]) `EXEC_NEWCYCLE
					`INSN_cc_C:	if (~`_F[4]) `EXEC_NEWCYCLE
					endcase
				end
			end
		2:	`EXEC_NEWCYCLE
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_JR_imm,`INSN_JRCC_imm: begin
		case (cycle)
		0:	begin /* type F */ end
		1:	tmp <= rdata;
		2:	`_PC <= `_PC + {tmp[7]?8'hFF:8'h00,tmp};
		endcase
	end
`endif