Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / LCDC.v
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1`define ADDR_LCDC 16'hFF40
2`define ADDR_STAT 16'hFF41
3`define ADDR_SCY 16'hFF42
4`define ADDR_SCX 16'hFF43
5`define ADDR_LY 16'hFF44
6`define ADDR_LYC 16'hFF45
7`define ADDR_DMA 16'hFF46
8`define ADDR_BGP 16'hFF47
9`define ADDR_OBP0 16'hFF48
10`define ADDR_OBP1 16'hFF49
11`define ADDR_WY 16'hFF4A
12`define ADDR_WX 16'hFF4B
13
14module LCDC(
15 input [15:0] addr,
16 inout [7:0] data,
17 input clk, // 8MHz clock
18 input wr, rd,
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19 output wire lcdcirq,
20 output wire vblankirq,
fe3dc890 21 output wire lcdclk, lcdvs, lcdhs,
ec727403 22 output reg [2:0] lcdr, lcdg, output reg [1:0] lcdb);
537e1f83 23
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24 /***** Bus latches *****/
25 reg rdlatch = 0;
26 reg [15:0] addrlatch = 0;
27
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28 /***** Needed prototypes *****/
29 wire [1:0] pixdata;
30
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31 /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
32 reg clk4 = 0;
33 always @(posedge clk)
2854e399 34 clk4 <= ~clk4;
537e1f83 35
00573fd5 36 /***** LCD control registers *****/
a42afaa9 37 reg [7:0] rLCDC = 8'h00;
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38 reg [7:0] rSTAT = 8'h00;
39 reg [7:0] rSCY = 8'b00;
40 reg [7:0] rSCX = 8'b00;
41 reg [7:0] rLYC = 8'b00;
42 reg [7:0] rDMA = 8'b00;
43 reg [7:0] rBGP = 8'b00;
44 reg [7:0] rOBP0 = 8'b00;
45 reg [7:0] rOBP1 = 8'b00;
46 reg [7:0] rWY = 8'b00;
47 reg [7:0] rWX = 8'b00;
48
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49 /***** Sync generation *****/
50
51 /* A complete cycle takes 456 clocks.
52 * VBlank lasts 4560 clocks (10 scanlines) -- LY = 144 - 153.
53 *
54 * Modes: 0 -> in hblank and OAM/VRAM available - present 207 clks
55 * 1 -> in vblank and OAM/VRAM available
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56 * 2 -> OAM in use - present 86 clks
57 * 3 -> OAM/VRAM in use - present 163 clks
58 * So, X = 0~162 is HActive,
59 * X = 163-369 is HBlank,
60 * X = 370-455 is HWhirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr.
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61 * [02:15:10] <Judge_> LY is updated near the 0 -> 2 transition
62 * [02:15:38] <Judge_> it seems to be updated internally first before it is visible in the LY register itself
63 * [02:15:40] <Judge_> some kind of delay
64 * [02:16:19] <Judge_> iirc it is updated about 4 cycles prior to mode 2
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65 */
66 reg [8:0] posx = 9'h000;
67 reg [7:0] posy = 8'h00;
39a68cde 68
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69 wire vraminuse = (posx < 163) && (posy < 144) && rLCDC[7];
70 wire oaminuse = (posx > 369) && (posy < 144) && rLCDC[7];
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71
72 wire display = (posx > 2) && (posx < 163) && (posy < 144);
73
537e1f83 74 wire [1:0] mode = (posy < 144) ?
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75 (vraminuse ? 2'b11 :
76 oaminuse ? 2'b10 :
77 2'b00)
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78 : 2'b01;
79
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80 wire [7:0] vxpos = rSCX + posx - 3;
81 wire [7:0] vypos = rSCY + posy;
82
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83 assign lcdvs = (posy == 153) && (posx == 2) && rLCDC[7];
84 assign lcdhs = (posx == 2) && rLCDC[7];
f356a735 85 assign lcdclk = clk4;
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86
87 wire [2:0] lcdr_ = display ? {pixdata[1] ? 3'b111 : 3'b000} : 3'b000;
88 wire [2:0] lcdg_ = display ? {pixdata[0] ? 3'b111 : 3'b000} : 3'b000;
89 wire [1:0] lcdb_ = display ? {(vypos < 8 || vxpos < 8) ? 2'b11 : 2'b00} : 2'b00;
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90
91 reg mode00irq = 0, mode01irq = 0, mode10irq = 0, lycirq = 0;
92 assign lcdcirq = (rSTAT[3] & mode00irq) | (rSTAT[4] & mode01irq) | (rSTAT[5] & mode10irq) | (rSTAT[6] & lycirq);
93 assign vblankirq = (posx == 0 && posy == 153);
94
2854e399 95 always @(posedge clk4)
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96 begin
97 if (posx == 455) begin
98 posx <= 0;
00573fd5 99 if (posy == 153) begin
537e1f83 100 posy <= 0;
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101 if (0 == rLYC)
102 lycirq <= 1;
103 end else begin
537e1f83 104 posy <= posy + 1;
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105 /* Check for vblank and generate an IRQ if needed. */
106 if (posy == 143) begin
107 mode01irq <= 1;
108 end
109 if ((posy + 1) == rLYC)
110 lycirq <= 1;
111
112 end
113 end else begin
537e1f83 114 posx <= posx + 1;
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115 if (posx == 165)
116 mode00irq <= 1;
117 else if (posx == 373)
118 mode10irq <= 1;
119 else begin
120 mode00irq <= 0;
121 mode01irq <= 0;
122 mode10irq <= 0;
123 end
124 lycirq <= 0;
125 end
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126
127 lcdr <= lcdr_;
128 lcdg <= lcdg_;
129 lcdb <= lcdb_;
537e1f83 130 end
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131
132 /***** Video RAM *****/
133 /* Base is 0x8000
134 *
135 * Tile data from 8000-8FFF or 8800-97FF
136 * Background tile maps 9800-9BFF or 9C00-9FFF
137 */
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138 reg [7:0] tiledatahigh [3071:0];
139 reg [7:0] tiledatalow [3071:0];
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140 reg [7:0] bgmap1 [1023:0];
141 reg [7:0] bgmap2 [1023:0];
142
143 // Upper five bits are Y coord, lower five bits are X coord
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144 // The new tile number is loaded when vxpos[2:0] is 3'b110
145 // The new tile data is loaded when vxpos[2:0] is 3'b111
39a68cde 146 // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
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147 wire [7:0] vxpos_ = vxpos + 1;
148 wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};
39a68cde 149 reg [7:0] tileno;
75be7c71 150 wire [10:0] tileaddr = {tileno, vypos[2:0]};
4d90f272 151 reg [7:0] tilehigh, tilelow;
b4f3ac35 152 wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
6d070aee 153 assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
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154
155 wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
156 wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
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157
158 wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
159 wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
39a68cde 160
8e2bb384 161 always @(posedge clk)
2854e399 162 begin
ec727403 163 if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
4d90f272 164 tileno <= bgmap1[bgmapaddr_in];
80ecd2fe 165 if (wr && decode_bgmap1 && ~vraminuse)
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166 bgmap1[bgmapaddr_in] <= data;
167 end
ec727403 168 if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
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169 tilehigh <= tiledatahigh[tileaddr_in];
170 tilelow <= tiledatalow[tileaddr_in];
80ecd2fe 171 if (wr && addr[0] && decode_tiledata && ~vraminuse)
4d90f272 172 tiledatahigh[tileaddr_in] <= data;
80ecd2fe 173 if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
4d90f272 174 tiledatalow[tileaddr_in] <= data;
39a68cde 175 end
2854e399 176 end
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177
178 /***** Bus interface *****/
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179 assign data = rdlatch ?
180 ((addrlatch == `ADDR_LCDC) ? rLCDC :
181 (addrlatch == `ADDR_STAT) ? {rSTAT[7:3], (rLYC == posy) ? 1'b1 : 1'b0, mode} :
182 (addrlatch == `ADDR_SCY) ? rSCY :
183 (addrlatch == `ADDR_SCX) ? rSCX :
184 (addrlatch == `ADDR_LY) ? posy :
185 (addrlatch == `ADDR_LYC) ? rLYC :
186 (addrlatch == `ADDR_BGP) ? rBGP :
187 (addrlatch == `ADDR_OBP0) ? rOBP0 :
188 (addrlatch == `ADDR_OBP1) ? rOBP1 :
189 (addrlatch == `ADDR_WY) ? rWY :
190 (addrlatch == `ADDR_WX) ? rWX :
191 (decode_tiledata && addrlatch[0]) ? tilehigh :
192 (decode_tiledata && ~addrlatch[0]) ? tilelow :
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193 (decode_bgmap1) ? tileno :
194 8'bzzzzzzzz) :
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195 8'bzzzzzzzz;
196
8e2bb384 197 always @(posedge clk)
537e1f83 198 begin
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199 rdlatch <= rd;
200 addrlatch <= addr;
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201 if (wr)
202 case (addr)
203 `ADDR_LCDC: rLCDC <= data;
204 `ADDR_STAT: rSTAT <= {data[7:2],rSTAT[1:0]};
205 `ADDR_SCY: rSCY <= data;
206 `ADDR_SCX: rSCX <= data;
207 `ADDR_LYC: rLYC <= data;
208 `ADDR_DMA: rDMA <= data;
209 `ADDR_BGP: rBGP <= data;
210 `ADDR_OBP0: rOBP0 <= data;
211 `ADDR_OBP1: rOBP1 <= data;
212 `ADDR_WY: rWY <= data;
213 `ADDR_WX: rWX <= data;
214 endcase
215 end
216endmodule
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