Gate off vraminuse, oaminuse, etc with wehther the LCD is powered on. Make sure to...
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
fe3dc890 9 reg [7:0] rom [1023:0];
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10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
fe3dc890 13 wire [7:0] odata = rom[address[10:0]];
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14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
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18module MiniRAM( /* XXX will need to go INSIDE the CPU for when we do DMA */
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
24 reg [7:0] ram [127:0];
25
26 wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27 reg [7:0] odata;
28 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29
30 always @(negedge clk)
31 begin
32 if (decode) // This has to go this way. The only way XST knows how to do
33 begin // block ram is chip select, write enable, and always
34 if (wr) // reading. "else if rd" does not cut it ...
35 ram[address[6:0]] <= data;
36 odata <= ram[address[6:0]];
37 end
38 end
c279b666 39endmodule
6bd4619b 40
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41module InternalRAM(
42 input [15:0] address,
43 inout [7:0] data,
44 input clk,
45 input wr, rd);
46
fe3dc890 47 // synthesis attribute ram_style of ram is block
616eebe0 48 reg [7:0] ram [8191:0];
a85b19a7 49
c87db60a 50 wire decode = address[15:13] == 3'b110;
a85b19a7 51 reg [7:0] odata;
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52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
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56 if (decode) // This has to go this way. The only way XST knows how to do
57 begin // block ram is chip select, write enable, and always
58 if (wr) // reading. "else if rd" does not cut it ...
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59 ram[address[12:0]] <= data;
60 odata <= ram[address[12:0]];
c87db60a 61 end
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62 end
63endmodule
64
65module Switches(
66 input [15:0] address,
67 inout [7:0] data,
68 input clk,
69 input wr, rd,
70 input [7:0] switches,
9c834ff2 71 output reg [7:0] ledout = 0);
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72
73 wire decode = address == 16'hFF51;
74 reg [7:0] odata;
75 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
76
77 always @(negedge clk)
78 begin
79 if (decode && rd)
80 odata <= switches;
81 else if (decode && wr)
82 ledout <= data;
83 end
84endmodule
85
86module CoreTop(
87 input xtal,
88 input [7:0] switches,
ff7fd7f2 89 input [3:0] buttons,
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90 output wire [7:0] leds,
91 output serio,
92 output wire [3:0] digits,
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93 output wire [7:0] seven,
94 output wire hs, vs,
95 output wire [2:0] r, g,
96 output wire [1:0] b);
a85b19a7 97
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98 wire xtalb, clk, vgaclk;
99 IBUFG iclkbuf(.O(xtalb), .I(xtal));
100 CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
101 pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
6c46357c 102
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103 wire [15:0] addr;
104 wire [7:0] data;
105 wire wr, rd;
f8db6448 106
00573fd5 107 wire irq, tmrirq, lcdcirq, vblankirq;
f8db6448 108 wire [7:0] jaddr;
6c46357c 109 wire [1:0] state;
179b4347 110
a85b19a7 111 GBZ80Core core(
179b4347 112 .clk(clk),
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113 .busaddress(addr),
114 .busdata(data),
115 .buswr(wr),
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116 .busrd(rd),
117 .irq(irq),
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118 .jaddr(jaddr),
119 .state(state));
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120
121 ROM rom(
122 .address(addr),
123 .data(data),
124 .clk(clk),
125 .wr(wr),
126 .rd(rd));
127
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128 wire lcdhs, lcdvs, lcdclk;
129 wire [2:0] lcdr, lcdg;
130 wire [1:0] lcdb;
131
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132 LCDC lcdc(
133 .addr(addr),
134 .data(data),
135 .clk(clk),
136 .wr(wr),
137 .rd(rd),
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138 .lcdcirq(lcdcirq),
139 .vblankirq(vblankirq),
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140 .lcdclk(lcdclk),
141 .lcdhs(lcdhs),
142 .lcdvs(lcdvs),
143 .lcdr(lcdr),
144 .lcdg(lcdg),
145 .lcdb(lcdb));
146
147 Framebuffer fb(
148 .lcdclk(lcdclk),
149 .lcdhs(lcdhs),
150 .lcdvs(lcdvs),
151 .lcdr(lcdr),
152 .lcdg(lcdg),
153 .lcdb(lcdb),
154 .vgaclk(vgaclk),
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155 .vgahs(hs),
156 .vgavs(vs),
157 .vgar(r),
158 .vgag(g),
159 .vgab(b));
537e1f83 160
a85b19a7 161 AddrMon amon(
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162 .addr(addr),
163 .clk(clk),
164 .digit(digits),
165 .out(seven),
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166 .freeze(buttons[0]),
167 .periods(
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168 (state == 2'b00) ? 4'b0010 :
169 (state == 2'b01) ? 4'b0001 :
170 (state == 2'b10) ? 4'b1000 :
171 4'b0100) );
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172
173 Switches sw(
174 .address(addr),
175 .data(data),
176 .clk(clk),
177 .wr(wr),
178 .rd(rd),
179 .ledout(leds),
fc443a4f 180 .switches(switches)
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181 );
182
06ad3a30 183 UART nouart ( /* no u */
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184 .clk(clk),
185 .wr(wr),
186 .rd(rd),
187 .addr(addr),
188 .data(data),
189 .serial(serio)
190 );
9aa931d1 191
eb0f2fe1 192 InternalRAM ram(
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193 .address(addr),
194 .data(data),
195 .clk(clk),
196 .wr(wr),
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197 .rd(rd)
198 );
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199
200 MiniRAM mram(
201 .address(addr),
202 .data(data),
203 .clk(clk),
204 .wr(wr),
205 .rd(rd)
206 );
06ad3a30 207
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208 Timer tmr(
209 .clk(clk),
210 .wr(wr),
211 .rd(rd),
212 .addr(addr),
213 .data(data),
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214 .irq(tmrirq)
215 );
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216
217 Interrupt intr(
218 .clk(clk),
219 .rd(rd),
220 .wr(wr),
221 .addr(addr),
222 .data(data),
00573fd5 223 .vblank(vblankirq),
537e1f83 224 .lcdc(lcdcirq),
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225 .tovf(tmrirq),
226 .serial(0),
227 .buttons(0),
228 .master(irq),
229 .jaddr(jaddr));
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230endmodule
231
232module TestBench();
62940da0 233 reg clk = 1;
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234 wire [15:0] addr;
235 wire [7:0] data;
236 wire wr, rd;
237
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238 wire irq, tmrirq;
239 wire [7:0] jaddr;
240
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241 wire [7:0] leds;
242 wire [7:0] switches;
a85b19a7 243
179b4347 244 always #62 clk <= ~clk;
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245 GBZ80Core core(
246 .clk(clk),
247 .busaddress(addr),
248 .busdata(data),
249 .buswr(wr),
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250 .busrd(rd),
251 .irq(irq),
252 .jaddr(jaddr));
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253
254 ROM rom(
255 .clk(clk),
256 .address(addr),
257 .data(data),
258 .wr(wr),
259 .rd(rd));
260
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261 InternalRAM ram(
262 .address(addr),
263 .data(data),
264 .clk(clk),
265 .wr(wr),
266 .rd(rd));
a85b19a7 267
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268 wire serio;
269 UART uart(
270 .addr(addr),
271 .data(data),
272 .clk(clk),
273 .wr(wr),
274 .rd(rd),
275 .serial(serio));
a85b19a7 276
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277 Timer tmr(
278 .clk(clk),
279 .wr(wr),
280 .rd(rd),
281 .addr(addr),
282 .data(data),
283 .irq(tmrirq));
284
285 Interrupt intr(
286 .clk(clk),
287 .rd(rd),
288 .wr(wr),
289 .addr(addr),
290 .data(data),
291 .vblank(0),
292 .lcdc(0),
293 .tovf(tmrirq),
294 .serial(0),
295 .buttons(0),
296 .master(irq),
297 .jaddr(jaddr));
298
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299 Switches sw(
300 .clk(clk),
301 .address(addr),
302 .data(data),
303 .wr(wr),
304 .rd(rd),
305 .switches(switches),
306 .ledout(leds));
a85b19a7 307endmodule
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