Fix add sp, imm8 *sweatdrop*
[fpgaboy.git] / core / insn_alu_ext.v
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1`define INSN_ALU_EXT 9'b100xxxxxx
2
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3`ifdef EXECUTE
4 `INSN_ALU_EXT: begin
5 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
6 `EXEC_READ(`_HL)
7 else begin
8 `EXEC_INC_PC
9 case (opcode[2:0])
10 `INSN_reg_A: tmp <= `_A;
11 `INSN_reg_B: tmp <= `_B;
12 `INSN_reg_C: tmp <= `_C;
13 `INSN_reg_D: tmp <= `_D;
14 `INSN_reg_E: tmp <= `_E;
15 `INSN_reg_H: tmp <= `_H;
16 `INSN_reg_L: tmp <= `_L;
17 `INSN_reg_dHL: tmp <= rdata;
18 endcase
19 end
20 end
21`endif
22
23`ifdef WRITEBACK
24 `INSN_ALU_EXT: begin
25 if (opcode[2:0] == `INSN_reg_dHL) begin
26 if(cycle == 0) begin end
27 else if(cycle == 1) begin
28 `EXEC_WRITE(`_HL, alu_res)
e7fe9dc2 29 `_F <= {f_res,`_F[3:0]};
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30 end else begin
31 `EXEC_NEWCYCLE
32 end
33 end else begin
34 case(opcode[2:0])
35 `INSN_reg_B: `_B <= alu_res;
36 `INSN_reg_C: `_C <= alu_res;
37 `INSN_reg_D: `_D <= alu_res;
38 `INSN_reg_E: `_E <= alu_res;
39 `INSN_reg_H: `_H <= alu_res;
40 `INSN_reg_L: `_L <= alu_res;
41 `INSN_reg_A: `_A <= alu_res;
42 `INSN_reg_dHL: begin end /* eat dicks */
43 endcase
44 `_F <= {f_res,`_F[3:0]};
45 `EXEC_NEWCYCLE
46 end
47 end
48`endif
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