Fix ld a, []

[fpgaboy.git] / GBZ80Core.v

`define REG_A	0
`define REG_B	1
`define REG_C	2
`define REG_D	3
`define REG_E	4
`define REG_F	5
`define REG_H	6
`define REG_L	7
`define REG_SPH	8
`define REG_SPL	9
`define REG_PCH	10
`define REG_PCL	11

`define _A	registers[`REG_A]
`define _B	registers[`REG_B]
`define _C	registers[`REG_C]
`define _D	registers[`REG_D]
`define _E	registers[`REG_E]
`define _F	registers[`REG_F]
`define _H	registers[`REG_H]
`define _L	registers[`REG_L]
`define _SPH	registers[`REG_SPH]
`define _SPL	registers[`REG_SPL]
`define _PCH	registers[`REG_PCH]
`define _PCL	registers[`REG_PCL]
`define _AF	{`_A, `_F}
`define _BC	{`_B, `_C}
`define _DE	{`_D, `_E}
`define _HL	{`_H, `_L}
`define _SP	{`_SPH, `_SPL}
`define _PC	{`_PCH, `_PCL}

`define FLAG_Z	8'b10000000
`define FLAG_N	8'b01000000
`define FLAG_H	8'b00100000
`define FLAG_C	8'b00010000

`define STATE_FETCH		2'h0
`define STATE_DECODE		2'h1
`define STATE_EXECUTE		2'h2
`define STATE_WRITEBACK		2'h3

`define INSN_LD_reg_imm8	8'b00xxx110
`define INSN_HALT		8'b01110110
`define INSN_LD_HL_reg		8'b01110xxx
`define INSN_LD_reg_HL		8'b01xxx110
`define INSN_LD_reg_reg		8'b01xxxxxx
`define INSN_LD_reg_imm16	8'b00xx0001
`define INSN_LD_SP_HL		8'b11111001
`define INSN_PUSH_reg		8'b11xx0101
`define INSN_POP_reg		8'b11xx0001
`define INSN_LDH_AC		8'b111x0010	// Either LDH A,(C) or LDH (C),A
`define INSN_LDx_AHL		8'b001xx010	// LDD/LDI A,(HL) / (HL),A
`define INSN_ALU8		8'b10xxxxxx	// 10 xxx yyy
`define INSN_ALU8IMM		8'b11xxx110
`define INSN_NOP		8'b00000000
`define INSN_RST		8'b11xxx111
`define INSN_RET		8'b110x1001	// 1 = RETI, 0 = RET
`define INSN_RETCC		8'b110xx000
`define INSN_CALL		8'b11001101
`define INSN_CALLCC		8'b110xx100	// Not that call/cc.
`define INSN_JP_imm		8'b11000011
`define INSN_JPCC_imm		8'b110xx010
`define INSN_ALU_A		8'b00xxx111
`define INSN_JP_HL		8'b11101001
`define INSN_JR_imm		8'b00011000
`define INSN_JRCC_imm		8'b001xx000
`define INSN_INCDEC16		8'b00xxx011
`define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
`define INSN_DI			8'b11110011
`define INSN_EI			8'b11111011
`define INSN_INCDEC_HL		8'b0011010x
`define INSN_INCDEC_reg8	8'b00xxx10x
`define INSN_LD8M_A		8'b111x0000	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
`define INSN_LD16M_A		8'b111x1010	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8

`define INSN_cc_NZ		2'b00
`define INSN_cc_Z		2'b01
`define INSN_cc_NC		2'b10
`define INSN_cc_C		2'b11

`define INSN_reg_A		3'b111
`define INSN_reg_B		3'b000
`define INSN_reg_C		3'b001
`define INSN_reg_D		3'b010
`define INSN_reg_E		3'b011
`define INSN_reg_H		3'b100
`define INSN_reg_L		3'b101
`define INSN_reg_dHL		3'b110
`define INSN_reg16_BC		2'b00
`define INSN_reg16_DE		2'b01
`define INSN_reg16_HL		2'b10
`define INSN_reg16_SP		2'b11
`define INSN_stack_AF		2'b11
`define INSN_stack_BC		2'b00
`define INSN_stack_DE		2'b01
`define INSN_stack_HL		2'b10
`define INSN_alu_ADD		3'b000
`define INSN_alu_ADC		3'b001
`define INSN_alu_SUB		3'b010
`define INSN_alu_SBC		3'b011
`define INSN_alu_AND		3'b100
`define INSN_alu_XOR		3'b101
`define INSN_alu_OR		3'b110
`define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
`define INSN_alu_RLCA		3'b000
`define INSN_alu_RRCA		3'b001
`define INSN_alu_RLA		3'b010
`define INSN_alu_RRA		3'b011
`define INSN_alu_DAA		3'b100
`define INSN_alu_CPL		3'b101
`define INSN_alu_SCF		3'b110
`define INSN_alu_CCF		3'b111

`define EXEC_INC_PC 		`_PC <= `_PC + 1;
`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end

module GBZ80Core(
	input clk,
	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
	inout [7:0] busdata,
	output reg buswr, output reg busrd,
	input irq, input [7:0] jaddr,
	output reg [1:0] state);
	
//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
	reg [2:0] cycle;					/* Cycle for instructions. */
	
	reg [7:0] registers[11:0];
	
	reg [15:0] address;				/* Address for the next bus operation. */
	
	reg [7:0] opcode;				/* Opcode from the current machine cycle. */
	
	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
	reg rd, wr, newcycle;
	
	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
	
	reg [7:0] buswdata;
	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
	
	reg ie, iedelay;
	
	initial begin
		registers[ 0] <= 0;
		registers[ 1] <= 0;
		registers[ 2] <= 0;
		registers[ 3] <= 0;
		registers[ 4] <= 0;
		registers[ 5] <= 0;
		registers[ 6] <= 0;
		registers[ 7] <= 0;
		registers[ 8] <= 0;
		registers[ 9] <= 0;
		registers[10] <= 0;
		registers[11] <= 0;
		rd <= 1;
		wr <= 0;
		newcycle <= 1;
		state <= 0;
		cycle <= 0;
		busrd <= 0;
		buswr <= 0;
		busaddress <= 0;
		ie <= 0;
		iedelay <= 0;
		opcode <= 0;
		state <= `STATE_WRITEBACK;
		cycle <= 0;
	end

	always @(posedge clk)
		case (state)
		`STATE_FETCH: begin
			if (newcycle) begin
				busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
				buswr <= 0;
				busrd <= 1;
			end else begin
				busaddress <= address;
				buswr <= wr;
				busrd <= rd;
				if (wr)
					buswdata <= wdata;
			end
			state <= `STATE_DECODE;
		end
		`STATE_DECODE: begin
			if (newcycle) begin
				if (ie && irq)
					opcode <= `INSN_VOP_INTR;
				else
					opcode <= busdata;
				rdata <= busdata;
				newcycle <= 0;
				cycle <= 0;
			end else begin
				if (rd) rdata <= busdata;
				cycle <= cycle + 1;
			end
			if (iedelay) begin
				ie <= 1;
				iedelay <= 0;
			end
			buswr <= 0;
			busrd <= 0;
			wr <= 0;
			rd <= 0;
			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
			wdata <= 8'bxxxxxxxx;
			state <= `STATE_EXECUTE;
		end
		`STATE_EXECUTE: begin
			casex (opcode)
			`define EXECUTE
			`include "allinsns.v"
			`undef EXECUTE
			default:
				$stop;
			endcase
			state <= `STATE_WRITEBACK;
		end
		`STATE_WRITEBACK: begin
			casex (opcode)
			`define WRITEBACK
			`include "allinsns.v"
			`undef WRITEBACK
			default:
				$stop;
			endcase
			state <= `STATE_FETCH;
		end
		endcase
endmodule