Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY...
[fpgaboy.git] / CPUDCM.v
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81358c71
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1////////////////////////////////////////////////////////////////////////////////
2// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
3////////////////////////////////////////////////////////////////////////////////
4// ____ ____
5// / /\/ /
6// /___/ \ / Vendor: Xilinx
7// \ \ \/ Version : 10.1
8// \ \ Application : xaw2verilog
9// / / Filename : CPUDCM.v
10// /___/ /\ Timestamp : 03/31/2008 23:51:44
11// \ \ / \
12// \___\/\___\
13//
14//Command: xaw2verilog -intstyle /home/joshua/projects/fpga/FPGABoy/CPUDCM.xaw -st CPUDCM.v
15//Design Name: CPUDCM
16//Device: xc3s500e-5fg320
17//
18// Module CPUDCM
19// Generated by Xilinx Architecture Wizard
20// Written for synthesis tool: XST
21// Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
22// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 4.90 ns
23`timescale 1ns / 1ps
24
25module CPUDCM(CLKIN_IN,
26 CLKFX_OUT,
27 CLKIN_IBUFG_OUT,
28 LOCKED_OUT);
29
30 input CLKIN_IN;
31 output CLKFX_OUT;
32 output CLKIN_IBUFG_OUT;
33 output LOCKED_OUT;
34
35 wire CLKFX_BUF;
36 wire CLKIN_IBUFG;
37 wire GND_BIT;
38
39 assign GND_BIT = 0;
40 assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
41 BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
42 .O(CLKFX_OUT));
81358c71 43 DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
fe3dc890 44 .CLKIN(CLKIN_IN),
81358c71
JW
45 .DSSEN(GND_BIT),
46 .PSCLK(GND_BIT),
47 .PSEN(GND_BIT),
48 .PSINCDEC(GND_BIT),
49 .RST(GND_BIT),
50 .CLKDV(),
51 .CLKFX(CLKFX_BUF),
52 .CLKFX180(),
53 .CLK0(),
54 .CLK2X(),
55 .CLK2X180(),
56 .CLK90(),
57 .CLK180(),
58 .CLK270(),
59 .LOCKED(LOCKED_OUT),
60 .PSDONE(),
61 .STATUS());
62 defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
63 defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
64 defparam DCM_SP_INST.CLKFX_DIVIDE = 25;
65 defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
66 defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
67 defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
68 defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
69 defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
70 defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
71 defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
72 defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
73 defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
74 defparam DCM_SP_INST.PHASE_SHIFT = 0;
75 defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
76endmodule
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