]> Joshua Wise's Git repositories - fpgaboy.git/blame - CoreTop.prj
Fix tileaddr bug. Make bus interface more explicit.
[fpgaboy.git] / CoreTop.prj
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4a393852
JW
1verilog work "Uart.v"
2verilog work "Timer.v"
3verilog work "Interrupt.v"
4verilog work "GBZ80Core.v"
5verilog work "CPUDCM.v"
6verilog work "7seg.v"
7verilog work "System.v"
8verilog work "LCDC.v"
9verilog work "Framebuffer.v"
10verilog work "pixDCM.v"
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