]> Joshua Wise's Git repositories - fpgaboy.git/blame - insn_push_reg.v
Add cut 1 of a cellram module
[fpgaboy.git] / insn_push_reg.v
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1`ifdef EXECUTE
2 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
3 case (cycle)
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4 0: case (opcode[5:4])
5 `INSN_stack_AF: `EXEC_WRITE(`_SP - 1, `_A)
6 `INSN_stack_BC: `EXEC_WRITE(`_SP - 1, `_B)
7 `INSN_stack_DE: `EXEC_WRITE(`_SP - 1, `_D)
8 `INSN_stack_HL: `EXEC_WRITE(`_SP - 1, `_H)
9 endcase
10 1: case (opcode[5:4])
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11 `INSN_stack_AF: `EXEC_WRITE(`_SP - 2, `_F)
12 `INSN_stack_BC: `EXEC_WRITE(`_SP - 2, `_C)
13 `INSN_stack_DE: `EXEC_WRITE(`_SP - 2, `_E)
14 `INSN_stack_HL: `EXEC_WRITE(`_SP - 2, `_L)
5c33c5c0 15 endcase
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16 2: begin /* Twiddle thumbs. */ end
17 3: begin
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18 `EXEC_NEWCYCLE
19 `EXEC_INC_PC
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20 end
21 endcase
22 end
23`endif
24
25`ifdef WRITEBACK
26 `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
27 case (cycle)
28 0: begin /* type F */ end
29 1: begin /* type F */ end
30 2: begin /* type F */ end
5c33c5c0 31 3: `_SP <= `_SP - 2;
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32 endcase
33 end
34`endif
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