Add cut 1 of a cellram module

[fpgaboy.git] / insn_bit.v

`ifdef EXECUTE
	`INSN_BIT: begin
		if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
			`EXEC_READ(`_HL)
		end else if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 2)) begin
			`EXEC_NEWCYCLE
		end else begin
			`EXEC_INC_PC
			case (opcode[2:0])
			`INSN_reg_A:	tmp <= `_A;
			`INSN_reg_B:	tmp <= `_B;
			`INSN_reg_C:	tmp <= `_C;
			`INSN_reg_D:	tmp <= `_D;
			`INSN_reg_E:	tmp <= `_E;
			`INSN_reg_H:	tmp <= `_H;
			`INSN_reg_L:	tmp <= `_L;
			`INSN_reg_dHL:	tmp <= rdata;
			endcase
			if (opcode[2:0] != `INSN_reg_dHL) begin
				`EXEC_NEWCYCLE
			end
		end
	end
`endif

`ifdef WRITEBACK
	`INSN_BIT: begin
		if ((opcode[2:0] != `INSN_reg_dHL) || (cycle == 1))
			`_F <= {~tmp[opcode[5:3]], 2'b01, `_F[4:0]};
	end
`endif