Add cut 1 of a cellram module

[fpgaboy.git] / 7seg.v

module AddrMon(
	input [15:0] addr,
	input clk,
	input [3:0] periods,
	output reg [3:0] digit,
	output wire [7:0] out,
	input freeze
	);

	reg [5:0] clkdv;
	reg [1:0] dcount;
	
	reg [15:0] latch = 0;

	wire [3:0] curval =
		(dcount == 2'b00) ? latch[3:0]  :
		(dcount == 2'b01) ? latch[7:4]  :
		(dcount == 2'b10) ? latch[11:8] :
		                    latch[15:12];
	
	reg [6:0] odigit;
	assign out = {odigit,
			~((dcount == 2'b00) ? periods[0] :
			  (dcount == 2'b01) ? periods[1] :
			  (dcount == 2'b10) ? periods[2] :
			                      periods[3]) };

	always @ (posedge clk) begin
		if (clkdv == 31) begin
			clkdv <= 0;
			dcount <= dcount + 1;

			case(dcount)
			2'b00: digit <= 4'b1110;
			2'b01: digit <= 4'b1101;
			2'b10: digit <= 4'b1011;
			2'b11: digit <= 4'b0111;
			endcase

			case(curval)
							/* ABCDEFGP */
			4'h0: odigit <= ~8'b1111110;
			4'h1: odigit <= ~8'b0110000;
			4'h2: odigit <= ~8'b1101101;
			4'h3: odigit <= ~8'b1111001;
			4'h4: odigit <= ~8'b0110011;
			4'h5: odigit <= ~8'b1011011;
			4'h6: odigit <= ~8'b1011111;
			4'h7: odigit <= ~8'b1110000;
			4'h8: odigit <= ~8'b1111111;
			4'h9: odigit <= ~8'b1111011;
			4'hA: odigit <= ~8'b1110111;
			4'hB: odigit <= ~8'b0011111;
			4'hC: odigit <= ~8'b1001110;
			4'hD: odigit <= ~8'b0111101;
			4'hE: odigit <= ~8'b1001111;
			4'hF: odigit <= ~8'b1000111;
			endcase
		end else
			clkdv <= clkdv + 1;
		
		if (~freeze)
			latch <= addr;
	end
endmodule