]> Joshua Wise's Git repositories - fpgaboy.git/blame - CoreTop.prj
Add a dirty hack to make the sim pipe directly to the readout script.
[fpgaboy.git] / CoreTop.prj
CommitLineData
4a393852
JW
1verilog work "Uart.v"
2verilog work "Timer.v"
3verilog work "Interrupt.v"
4verilog work "GBZ80Core.v"
5verilog work "CPUDCM.v"
6verilog work "7seg.v"
7verilog work "System.v"
8verilog work "LCDC.v"
9verilog work "Framebuffer.v"
6ba4cfea
JW
10verilog work "pixDCM.v"
11verilog work "Sound1.v"
12verilog work "Sound2.v"
13verilog work "Soundcore.v"
This page took 0.024276 seconds and 4 git commands to generate.