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[fpgaboy.git] / Soundcore.v
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1`define ADDR_NR50 16'hFF24
2`define ADDR_NR51 16'hFF25
3`define ADDR_NR52 16'hFF26
4
5module Soundcore(
6 input core_clk,
7 input wr,
8 input rd,
9 input [15:0] addr,
10 inout [7:0] data,
11 output reg snd_data_l,
12 output reg snd_data_r
13 );
14
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15 reg [7:0] nr50 = 8'h00, nr51 = 8'h00, nr52 = 8'hF0;
16 reg [3:0] pwmcnt = 4'b0000;
17 reg [4:0] cntclk = 5'b00000;
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18 reg [13:0] lenclk;
19 wire [3:0] sndout1,sndout2,sndout3,sndout4;
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20 wire [3:0] right_snd =
21 (nr51[0] ? sndout1 : 4'b0) +
22 (nr51[1] ? sndout2 : 4'b0) +
23 (nr51[2] ? sndout3 : 4'b0) +
24 (nr51[3] ? sndout4 : 4'b0);
25 wire [3:0] left_snd =
26 (nr51[4] ? sndout1 : 4'b0) +
27 (nr51[5] ? sndout2 : 4'b0) +
28 (nr51[6] ? sndout3 : 4'b0) +
29 (nr51[7] ? sndout4 : 4'b0);
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30 assign sndout3 = 0;
31 assign sndout4 = 0;
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32
33 reg rdlatch;
34 reg [15:0] addrlatch;
35
36 assign data = rdlatch ?
37 addrlatch == `ADDR_NR50 ? nr50 :
38 addrlatch == `ADDR_NR51 ? nr51 :
39 addrlatch == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
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40 : 8'bzzzzzzzz;
41
68ce013e 42 always @ (posedge core_clk) begin
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43 rdlatch <= rd;
44 addrlatch <= addr;
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45 if(wr) begin
46 case(addr)
47 `ADDR_NR50: nr50 <= data;
48 `ADDR_NR51: nr51 <= data;
01878f5f 49 `ADDR_NR52: nr52 <= {data[7],7'b1111111};
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50 endcase
51 end
52 cntclk <= cntclk + 1;
53 lenclk <= lenclk + 1;
54 pwmcnt <= pwmcnt + 1;
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55 snd_data_l <= (pwmcnt <= left_snd) ? 1 : 0;
56 snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
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57 end
58
09c1936c 59 Sound1 s1(
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60 .core_clk(core_clk),
61 .wr(wr),
62 .rd(rd),
63 .addr(addr),
64 .data(data),
65 .cntclk(cntclk[4]),
66 .lenclk(lenclk[13]),
01878f5f 67 .en(nr52[7]),
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68 .snd_data(sndout1)
69 );
70
09c1936c 71 Sound2 s2(
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72 .core_clk(core_clk),
73 .wr(wr),
74 .rd(rd),
75 .addr(addr),
76 .data(data),
77 .cntclk(cntclk[4]),
78 .lenclk(lenclk[13]),
01878f5f 79 .en(nr52[7]),
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80 .snd_data(sndout2)
81 );
82
83endmodule
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