[fpgaboy.git] / insn_ld_reg_hl.v

`ifdef EXECUTE
	`INSN_LD_reg_HL: begin
		case(cycle)
		0:	begin
				address <= {registers[`REG_H], registers[`REG_L]};
				rd <= 1;
			end
		1:	begin
				tmp <= rdata;
				`EXEC_INC_PC;
				`EXEC_NEWCYCLE;
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_reg_HL: begin
		case (cycle)
		0:	begin end
		1:	begin
				case (opcode[5:3])
				`INSN_reg_A:	registers[`REG_A] <= tmp;
				`INSN_reg_B:	registers[`REG_B] <= tmp;
				`INSN_reg_C:	registers[`REG_C] <= tmp;
				`INSN_reg_D:	registers[`REG_D] <= tmp;
				`INSN_reg_E:	registers[`REG_E] <= tmp;
				`INSN_reg_H:	registers[`REG_H] <= tmp;
				`INSN_reg_L:	registers[`REG_L] <= tmp;
				endcase
			end
		endcase
	end
`endif
Commit	Line	Data
81358c71 JW	1	`ifdef EXECUTE
	2	`INSN_LD_reg_HL: begin
	3	case(cycle)
	4	0: begin
	5	address <= {registers[`REG_H], registers[`REG_L]};
	6	rd <= 1;
	7	end
	8	1: begin
	9	tmp <= rdata;
	10	`EXEC_INC_PC;
	11	`EXEC_NEWCYCLE;
	12	end
	13	endcase
	14	end
	15	`endif
	16
	17	`ifdef WRITEBACK
	18	`INSN_LD_reg_HL: begin
	19	case (cycle)
	20	0: begin end
	21	1: begin
	22	case (opcode[5:3])
	23	`INSN_reg_A: registers[`REG_A] <= tmp;
	24	`INSN_reg_B: registers[`REG_B] <= tmp;
	25	`INSN_reg_C: registers[`REG_C] <= tmp;
	26	`INSN_reg_D: registers[`REG_D] <= tmp;
	27	`INSN_reg_E: registers[`REG_E] <= tmp;
	28	`INSN_reg_H: registers[`REG_H] <= tmp;
	29	`INSN_reg_L: registers[`REG_L] <= tmp;
	30	endcase
	31	end
	32	endcase
	33	end
	34	`endif