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[fpgaboy.git] / core / insn_ld_reg_hl.v
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1`define INSN_LD_reg_HL 9'b001xxx110
2
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3`ifdef EXECUTE
4 `INSN_LD_reg_HL: begin
5 case(cycle)
5c33c5c0 6 0: `EXEC_READ(`_HL)
81358c71 7 1: begin
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8 `EXEC_INC_PC
9 `EXEC_NEWCYCLE
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10 end
11 endcase
12 end
13`endif
14
15`ifdef WRITEBACK
16 `INSN_LD_reg_HL: begin
17 case (cycle)
18 0: begin end
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19 1: case (opcode[5:3])
20 `INSN_reg_A: `_A <= rdata;
21 `INSN_reg_B: `_B <= rdata;
22 `INSN_reg_C: `_C <= rdata;
23 `INSN_reg_D: `_D <= rdata;
24 `INSN_reg_E: `_E <= rdata;
25 `INSN_reg_H: `_H <= rdata;
26 `INSN_reg_L: `_L <= rdata;
27 endcase
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28 endcase
29 end
30`endif
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