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[fpgaboy.git] / core / insn_ld_nn_sp.v

`define INSN_LD_NN_SP		9'b000001000

`ifdef EXECUTE
	`INSN_LD_NN_SP: begin
		case (cycle)
		0:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 16'h0001)
			end
		1:	begin
				`EXEC_INC_PC
				`EXEC_READ(`_PC + 16'h0001)
			end
		2:	begin
				`EXEC_WRITE(({rdata, tmp}), `_SPL)
			end
		3:	begin
				`EXEC_WRITE(({tmp, tmp2}), `_SPH)
			end
		4:	begin
				`EXEC_NEWCYCLE
				`EXEC_INC_PC
			end
		endcase
	end
`endif

`ifdef WRITEBACK
	`INSN_LD_NN_SP: begin
		case (cycle)
		0:	begin end
		1:	tmp <= rdata;
		2:	{tmp, tmp2} <= {rdata, tmp} + 1;
		3:	begin end
		4:	begin end
		endcase
	end
`endif